forked from OSchip/llvm-project
[ARM] GlobalISel: Support frem for 32-bit values
Legalize to a libcall. On this occasion, also start allowing soft float subtargets. For the moment G_FREM is the only legal floating point operation for them. llvm-svn: 299753
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@ -333,10 +333,6 @@ bool ARMCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
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if (Subtarget->isThumb())
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return false;
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// FIXME: Support soft float (when we're ready to generate libcalls)
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if (Subtarget->useSoftFloat() || !Subtarget->hasVFP2())
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return false;
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for (auto &Arg : F.args())
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if (!isSupportedType(DL, TLI, Arg.getType()))
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return false;
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@ -57,7 +57,7 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
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setAction({G_CONSTANT, s32}, Legal);
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if (ST.hasVFP2()) {
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if (!ST.useSoftFloat() && ST.hasVFP2()) {
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setAction({G_FADD, s32}, Legal);
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setAction({G_FADD, s64}, Legal);
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@ -65,5 +65,7 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
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setAction({G_STORE, s64}, Legal);
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}
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setAction({G_FREM, s32}, Libcall);
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computeTables();
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}
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@ -0,0 +1,11 @@
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; RUN: llc -mtriple arm-unknown -mattr=+vfp2 -float-abi=hard -global-isel %s -o - | FileCheck %s
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; RUN: llc -mtriple arm-unknown -mattr=+vfp2 -float-abi=soft -global-isel %s -o - | FileCheck %s
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; RUN: llc -mtriple arm-unknwon -float-abi=soft -global-isel %s -o - | FileCheck %s
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define arm_aapcscc float @test_frem_float(float %x, float %y) {
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; CHECK-LABEL: test_frem_float:
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; CHECK: blx fmodf
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%r = frem float %x, %y
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ret float %r
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}
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@ -0,0 +1,37 @@
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# RUN: llc -mtriple arm-- -mattr=+vfp2 -float-abi=hard -global-isel -run-pass=legalizer %s -o - | FileCheck %s
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# RUN: llc -mtriple arm-- -mattr=+vfp2 -float-abi=soft -global-isel -run-pass=legalizer %s -o - | FileCheck %s
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# RUN: llc -mtriple arm-- -float-abi=soft -global-isel -run-pass=legalizer %s -o - | FileCheck %s
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--- |
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define void @test_frem_float() { ret void }
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...
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---
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name: test_frem_float
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# CHECK-LABEL: name: test_frem_float
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
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; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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; CHECK: ADJCALLSTACKDOWN
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; CHECK-DAG: %r0 = COPY [[X]]
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; CHECK-DAG: %r1 = COPY [[Y]]
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; CHECK: BLX $fmodf, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; CHECK: [[R:%[0-9]+]](s32) = COPY %r0
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; CHECK: ADJCALLSTACKUP
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%2(s32) = G_FREM %0, %1
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; CHECK: %r0 = COPY [[R]]
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%r0 = COPY %2(s32)
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BX_RET 14, _, implicit %r0
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...
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