[ARM] GlobalISel: Support frem for 32-bit values

Legalize to a libcall.
On this occasion, also start allowing soft float subtargets. For the
moment G_FREM is the only legal floating point operation for them.

llvm-svn: 299753
This commit is contained in:
Diana Picus 2017-04-07 09:41:39 +00:00
parent 434b333afd
commit a5bab61a8d
4 changed files with 51 additions and 5 deletions

View File

@ -333,10 +333,6 @@ bool ARMCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
if (Subtarget->isThumb())
return false;
// FIXME: Support soft float (when we're ready to generate libcalls)
if (Subtarget->useSoftFloat() || !Subtarget->hasVFP2())
return false;
for (auto &Arg : F.args())
if (!isSupportedType(DL, TLI, Arg.getType()))
return false;

View File

@ -57,7 +57,7 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
setAction({G_CONSTANT, s32}, Legal);
if (ST.hasVFP2()) {
if (!ST.useSoftFloat() && ST.hasVFP2()) {
setAction({G_FADD, s32}, Legal);
setAction({G_FADD, s64}, Legal);
@ -65,5 +65,7 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
setAction({G_STORE, s64}, Legal);
}
setAction({G_FREM, s32}, Libcall);
computeTables();
}

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@ -0,0 +1,11 @@
; RUN: llc -mtriple arm-unknown -mattr=+vfp2 -float-abi=hard -global-isel %s -o - | FileCheck %s
; RUN: llc -mtriple arm-unknown -mattr=+vfp2 -float-abi=soft -global-isel %s -o - | FileCheck %s
; RUN: llc -mtriple arm-unknwon -float-abi=soft -global-isel %s -o - | FileCheck %s
define arm_aapcscc float @test_frem_float(float %x, float %y) {
; CHECK-LABEL: test_frem_float:
; CHECK: blx fmodf
%r = frem float %x, %y
ret float %r
}

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@ -0,0 +1,37 @@
# RUN: llc -mtriple arm-- -mattr=+vfp2 -float-abi=hard -global-isel -run-pass=legalizer %s -o - | FileCheck %s
# RUN: llc -mtriple arm-- -mattr=+vfp2 -float-abi=soft -global-isel -run-pass=legalizer %s -o - | FileCheck %s
# RUN: llc -mtriple arm-- -float-abi=soft -global-isel -run-pass=legalizer %s -o - | FileCheck %s
--- |
define void @test_frem_float() { ret void }
...
---
name: test_frem_float
# CHECK-LABEL: name: test_frem_float
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: %r0, %r1
; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
%0(s32) = COPY %r0
%1(s32) = COPY %r1
; CHECK: ADJCALLSTACKDOWN
; CHECK-DAG: %r0 = COPY [[X]]
; CHECK-DAG: %r1 = COPY [[Y]]
; CHECK: BLX $fmodf, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
; CHECK: [[R:%[0-9]+]](s32) = COPY %r0
; CHECK: ADJCALLSTACKUP
%2(s32) = G_FREM %0, %1
; CHECK: %r0 = COPY [[R]]
%r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0
...