forked from OSchip/llvm-project
[AArch64][SVE] Add support for DestructiveBinary and DestructiveBinaryComm DestructiveInstTypes
Add support for DestructiveBinaryComm DestructiveInstType, as well as the lowering code to expand the new Pseudos into the final movprfx+instruction pairs. Differential Revision: https://reviews.llvm.org/D73711
This commit is contained in:
Cameron McInally
parent
b72f1448ce
commit
a5b22b768f
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@ -68,6 +68,8 @@ private:
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bool expandMOVImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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unsigned BitSize);
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bool expand_DestructiveOp(MachineInstr &MI, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI);
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bool expandCMP_SWAP(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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unsigned LdarOp, unsigned StlrOp, unsigned CmpOp,
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unsigned ExtendImm, unsigned ZeroReg,
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@ -344,6 +346,176 @@ bool AArch64ExpandPseudo::expandCMP_SWAP_128(
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return true;
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}
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/// \brief Expand Pseudos to Instructions with destructive operands.
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///
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/// This mechanism uses MOVPRFX instructions for zeroing the false lanes
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/// or for fixing relaxed register allocation conditions to comply with
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/// the instructions register constraints. The latter case may be cheaper
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/// than setting the register constraints in the register allocator,
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/// since that will insert regular MOV instructions rather than MOVPRFX.
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///
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/// Example (after register allocation):
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///
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/// FSUB_ZPZZ_ZERO_B Z0, Pg, Z1, Z0
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///
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/// * The Pseudo FSUB_ZPZZ_ZERO_B maps to FSUB_ZPmZ_B.
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/// * We cannot map directly to FSUB_ZPmZ_B because the register
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/// constraints of the instruction are not met.
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/// * Also the _ZERO specifies the false lanes need to be zeroed.
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///
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/// We first try to see if the destructive operand == result operand,
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/// if not, we try to swap the operands, e.g.
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///
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/// FSUB_ZPmZ_B Z0, Pg/m, Z0, Z1
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///
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/// But because FSUB_ZPmZ is not commutative, this is semantically
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/// different, so we need a reverse instruction:
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///
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/// FSUBR_ZPmZ_B Z0, Pg/m, Z0, Z1
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///
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/// Then we implement the zeroing of the false lanes of Z0 by adding
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/// a zeroing MOVPRFX instruction:
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///
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/// MOVPRFX_ZPzZ_B Z0, Pg/z, Z0
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/// FSUBR_ZPmZ_B Z0, Pg/m, Z0, Z1
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///
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/// Note that this can only be done for _ZERO or _UNDEF variants where
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/// we can guarantee the false lanes to be zeroed (by implementing this)
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/// or that they are undef (don't care / not used), otherwise the
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/// swapping of operands is illegal because the operation is not
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/// (or cannot be emulated to be) fully commutative.
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bool AArch64ExpandPseudo::expand_DestructiveOp(
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MachineInstr &MI,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI) {
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unsigned Opcode = AArch64::getSVEPseudoMap(MI.getOpcode());
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uint64_t DType = TII->get(Opcode).TSFlags & AArch64::DestructiveInstTypeMask;
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uint64_t FalseLanes = MI.getDesc().TSFlags & AArch64::FalseLanesMask;
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bool FalseZero = FalseLanes == AArch64::FalseLanesZero;
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unsigned DstReg = MI.getOperand(0).getReg();
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bool DstIsDead = MI.getOperand(0).isDead();
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if (DType == AArch64::DestructiveBinary)
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assert(DstReg != MI.getOperand(3).getReg());
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bool UseRev = false;
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unsigned PredIdx, DOPIdx, SrcIdx;
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switch (DType) {
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case AArch64::DestructiveBinaryComm:
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case AArch64::DestructiveBinaryCommWithRev:
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if (DstReg == MI.getOperand(3).getReg()) {
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// FSUB Zd, Pg, Zs1, Zd ==> FSUBR Zd, Pg/m, Zd, Zs1
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std::tie(PredIdx, DOPIdx, SrcIdx) = std::make_tuple(1, 3, 2);
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UseRev = true;
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break;
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}
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LLVM_FALLTHROUGH;
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case AArch64::DestructiveBinary:
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std::tie(PredIdx, DOPIdx, SrcIdx) = std::make_tuple(1, 2, 3);
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break;
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default:
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llvm_unreachable("Unsupported Destructive Operand type");
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}
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#ifndef NDEBUG
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// MOVPRFX can only be used if the destination operand
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// is the destructive operand, not as any other operand,
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// so the Destructive Operand must be unique.
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bool DOPRegIsUnique = false;
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switch (DType) {
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case AArch64::DestructiveBinaryComm:
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case AArch64::DestructiveBinaryCommWithRev:
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DOPRegIsUnique =
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DstReg != MI.getOperand(DOPIdx).getReg() ||
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MI.getOperand(DOPIdx).getReg() != MI.getOperand(SrcIdx).getReg();
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break;
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}
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assert (DOPRegIsUnique && "The destructive operand should be unique");
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#endif
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// Resolve the reverse opcode
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if (UseRev) {
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if (AArch64::getSVERevInstr(Opcode) != -1)
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Opcode = AArch64::getSVERevInstr(Opcode);
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else if (AArch64::getSVEOrigInstr(Opcode) != -1)
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Opcode = AArch64::getSVEOrigInstr(Opcode);
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}
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// Get the right MOVPRFX
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uint64_t ElementSize = TII->getElementSizeForOpcode(Opcode);
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unsigned MovPrfx, MovPrfxZero;
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switch (ElementSize) {
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case AArch64::ElementSizeNone:
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case AArch64::ElementSizeB:
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MovPrfx = AArch64::MOVPRFX_ZZ;
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MovPrfxZero = AArch64::MOVPRFX_ZPzZ_B;
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break;
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case AArch64::ElementSizeH:
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MovPrfx = AArch64::MOVPRFX_ZZ;
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MovPrfxZero = AArch64::MOVPRFX_ZPzZ_H;
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break;
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case AArch64::ElementSizeS:
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MovPrfx = AArch64::MOVPRFX_ZZ;
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MovPrfxZero = AArch64::MOVPRFX_ZPzZ_S;
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break;
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case AArch64::ElementSizeD:
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MovPrfx = AArch64::MOVPRFX_ZZ;
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MovPrfxZero = AArch64::MOVPRFX_ZPzZ_D;
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break;
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default:
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llvm_unreachable("Unsupported ElementSize");
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}
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//
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// Create the destructive operation (if required)
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//
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MachineInstrBuilder PRFX, DOP;
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if (FalseZero) {
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assert(ElementSize != AArch64::ElementSizeNone &&
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"This instruction is unpredicated");
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// Merge source operand into destination register
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PRFX = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(MovPrfxZero))
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.addReg(DstReg, RegState::Define)
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.addReg(MI.getOperand(PredIdx).getReg())
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.addReg(MI.getOperand(DOPIdx).getReg());
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// After the movprfx, the destructive operand is same as Dst
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DOPIdx = 0;
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} else if (DstReg != MI.getOperand(DOPIdx).getReg()) {
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PRFX = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(MovPrfx))
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.addReg(DstReg, RegState::Define)
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.addReg(MI.getOperand(DOPIdx).getReg());
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DOPIdx = 0;
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}
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//
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// Create the destructive operation
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//
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DOP = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opcode))
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.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead));
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switch (DType) {
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case AArch64::DestructiveBinaryComm:
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case AArch64::DestructiveBinaryCommWithRev:
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DOP.add(MI.getOperand(PredIdx))
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.addReg(MI.getOperand(DOPIdx).getReg(), RegState::Kill)
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.add(MI.getOperand(SrcIdx));
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break;
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}
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if (PRFX) {
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finalizeBundle(MBB, PRFX->getIterator(), MBBI->getIterator());
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transferImpOps(MI, PRFX, DOP);
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} else
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transferImpOps(MI, DOP, DOP);
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MI.eraseFromParent();
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return true;
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}
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bool AArch64ExpandPseudo::expandSetTagLoop(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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@ -425,6 +597,17 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &NextMBBI) {
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MachineInstr &MI = *MBBI;
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unsigned Opcode = MI.getOpcode();
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// Check if we can expand the destructive op
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int OrigInstr = AArch64::getSVEPseudoMap(MI.getOpcode());
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if (OrigInstr != -1) {
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auto &Orig = TII->get(OrigInstr);
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if ((Orig.TSFlags & AArch64::DestructiveInstTypeMask)
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!= AArch64::NotDestructive) {
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return expand_DestructiveOp(MI, MBB, MBBI);
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}
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}
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switch (Opcode) {
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default:
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break;
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@ -162,6 +162,25 @@ public:
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return false;
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}
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bool SelectDupZero(SDValue N) {
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switch(N->getOpcode()) {
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case AArch64ISD::DUP:
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case ISD::SPLAT_VECTOR: {
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auto Opnd0 = N->getOperand(0);
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if (auto CN = dyn_cast<ConstantSDNode>(Opnd0))
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if (CN->isNullValue())
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return true;
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if (auto CN = dyn_cast<ConstantFPSDNode>(Opnd0))
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if (CN->isZero())
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return true;
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}
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default:
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break;
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}
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return false;
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}
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template<MVT::SimpleValueType VT>
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bool SelectSVEAddSubImm(SDValue N, SDValue &Imm, SDValue &Shift) {
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return SelectSVEAddSubImm(N, VT, Imm, Shift);
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@ -22,13 +22,27 @@ def NormalFrm : Format<1>; // Do we need any others?
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// Enum describing whether an instruction is
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// destructive in its first source operand.
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class DestructiveInstTypeEnum<bits<1> val> {
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bits<1> Value = val;
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class DestructiveInstTypeEnum<bits<4> val> {
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bits<4> Value = val;
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}
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def NotDestructive : DestructiveInstTypeEnum<0>;
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def NotDestructive : DestructiveInstTypeEnum<0>;
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// Destructive in its first operand and can be MOVPRFX'd, but has no other
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// special properties.
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def DestructiveOther : DestructiveInstTypeEnum<1>;
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def DestructiveOther : DestructiveInstTypeEnum<1>;
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def DestructiveUnary : DestructiveInstTypeEnum<2>;
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def DestructiveBinaryImm : DestructiveInstTypeEnum<3>;
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def DestructiveBinaryShImmUnpred : DestructiveInstTypeEnum<4>;
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def DestructiveBinary : DestructiveInstTypeEnum<5>;
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def DestructiveBinaryComm : DestructiveInstTypeEnum<6>;
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def DestructiveBinaryCommWithRev : DestructiveInstTypeEnum<7>;
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def DestructiveTernaryCommWithRev : DestructiveInstTypeEnum<8>;
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class FalseLanesEnum<bits<2> val> {
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bits<2> Value = val;
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}
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def FalseLanesNone : FalseLanesEnum<0>;
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def FalseLanesZero : FalseLanesEnum<1>;
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def FalseLanesUndef : FalseLanesEnum<2>;
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// AArch64 Instruction Format
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class AArch64Inst<Format f, string cstr> : Instruction {
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@ -46,10 +60,12 @@ class AArch64Inst<Format f, string cstr> : Instruction {
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bits<2> Form = F.Value;
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// Defaults
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FalseLanesEnum FalseLanes = FalseLanesNone;
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DestructiveInstTypeEnum DestructiveInstType = NotDestructive;
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ElementSizeEnum ElementSize = ElementSizeNone;
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let TSFlags{3} = DestructiveInstType.Value;
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let TSFlags{8-7} = FalseLanes.Value;
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let TSFlags{6-3} = DestructiveInstType.Value;
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let TSFlags{2-0} = ElementSize.Value;
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let Pattern = [];
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@ -119,11 +119,25 @@ unsigned AArch64InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
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case AArch64::SPACE:
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NumBytes = MI.getOperand(1).getImm();
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break;
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case TargetOpcode::BUNDLE:
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NumBytes = getInstBundleLength(MI);
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break;
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}
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return NumBytes;
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}
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unsigned AArch64InstrInfo::getInstBundleLength(const MachineInstr &MI) const {
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unsigned Size = 0;
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MachineBasicBlock::const_instr_iterator I = MI.getIterator();
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MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
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while (++I != E && I->isInsideBundle()) {
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assert(!I->isBundle() && "No nested bundle!");
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Size += getInstSizeInBytes(*I);
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}
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return Size;
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}
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static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
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SmallVectorImpl<MachineOperand> &Cond) {
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// Block ends with fall-through condbranch.
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@ -6680,5 +6694,10 @@ AArch64InstrInfo::describeLoadedValue(const MachineInstr &MI,
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return TargetInstrInfo::describeLoadedValue(MI, Reg);
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}
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uint64_t AArch64InstrInfo::getElementSizeForOpcode(unsigned Opc) const {
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return get(Opc).TSFlags & AArch64::ElementSizeMask;
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}
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#define GET_INSTRINFO_HELPERS
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#define GET_INSTRMAP_INFO
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#include "AArch64GenInstrInfo.inc"
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@ -271,6 +271,8 @@ public:
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MachineBasicBlock::iterator &It, MachineFunction &MF,
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const outliner::Candidate &C) const override;
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bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
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/// Returns the vector element size (B, H, S or D) of an SVE opcode.
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uint64_t getElementSizeForOpcode(unsigned Opc) const;
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/// Returns true if the instruction has a shift by immediate that can be
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/// executed in one cycle less.
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static bool isFalkorShiftExtFast(const MachineInstr &MI);
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@ -295,6 +297,8 @@ protected:
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isCopyInstrImpl(const MachineInstr &MI) const override;
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private:
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unsigned getInstBundleLength(const MachineInstr &MI) const;
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/// Sets the offsets on outlined instructions in \p MBB which use SP
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/// so that they will be valid post-outlining.
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///
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@ -381,7 +385,8 @@ static inline bool isIndirectBranchOpcode(int Opc) {
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// struct TSFlags {
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#define TSFLAG_ELEMENT_SIZE_TYPE(X) (X) // 3-bits
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#define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 1-bit
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#define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 4-bit
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#define TSFLAG_FALSE_LANE_TYPE(X) ((X) << 7) // 2-bits
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// }
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namespace AArch64 {
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@ -396,13 +401,31 @@ enum ElementSizeType {
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};
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enum DestructiveInstType {
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DestructiveInstTypeMask = TSFLAG_DESTRUCTIVE_INST_TYPE(0x1),
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NotDestructive = TSFLAG_DESTRUCTIVE_INST_TYPE(0x0),
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DestructiveOther = TSFLAG_DESTRUCTIVE_INST_TYPE(0x1),
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DestructiveInstTypeMask = TSFLAG_DESTRUCTIVE_INST_TYPE(0xf),
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NotDestructive = TSFLAG_DESTRUCTIVE_INST_TYPE(0x0),
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DestructiveOther = TSFLAG_DESTRUCTIVE_INST_TYPE(0x1),
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DestructiveUnary = TSFLAG_DESTRUCTIVE_INST_TYPE(0x2),
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DestructiveBinaryImm = TSFLAG_DESTRUCTIVE_INST_TYPE(0x3),
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DestructiveBinaryShImmUnpred = TSFLAG_DESTRUCTIVE_INST_TYPE(0x4),
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DestructiveBinary = TSFLAG_DESTRUCTIVE_INST_TYPE(0x5),
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DestructiveBinaryComm = TSFLAG_DESTRUCTIVE_INST_TYPE(0x6),
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DestructiveBinaryCommWithRev = TSFLAG_DESTRUCTIVE_INST_TYPE(0x7),
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DestructiveTernaryCommWithRev = TSFLAG_DESTRUCTIVE_INST_TYPE(0x8),
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};
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enum FalseLaneType {
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FalseLanesMask = TSFLAG_FALSE_LANE_TYPE(0x3),
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FalseLanesZero = TSFLAG_FALSE_LANE_TYPE(0x1),
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FalseLanesUndef = TSFLAG_FALSE_LANE_TYPE(0x2),
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};
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#undef TSFLAG_ELEMENT_SIZE_TYPE
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#undef TSFLAG_DESTRUCTIVE_INST_TYPE
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#undef TSFLAG_FALSE_LANE_TYPE
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int getSVEPseudoMap(uint16_t Opcode);
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int getSVERevInstr(uint16_t Opcode);
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int getSVEOrigInstr(uint16_t Opcode);
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}
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} // end namespace llvm
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@ -239,19 +239,32 @@ let Predicates = [HasSVE] in {
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defm FMAX_ZPmI : sve_fp_2op_i_p_zds<0b110, "fmax", sve_fpimm_zero_one>;
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defm FMIN_ZPmI : sve_fp_2op_i_p_zds<0b111, "fmin", sve_fpimm_zero_one>;
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defm FADD_ZPmZ : sve_fp_2op_p_zds<0b0000, "fadd", int_aarch64_sve_fadd>;
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defm FSUB_ZPmZ : sve_fp_2op_p_zds<0b0001, "fsub", int_aarch64_sve_fsub>;
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defm FMUL_ZPmZ : sve_fp_2op_p_zds<0b0010, "fmul", int_aarch64_sve_fmul>;
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defm FSUBR_ZPmZ : sve_fp_2op_p_zds<0b0011, "fsubr", int_aarch64_sve_fsubr>;
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defm FMAXNM_ZPmZ : sve_fp_2op_p_zds<0b0100, "fmaxnm", int_aarch64_sve_fmaxnm>;
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defm FMINNM_ZPmZ : sve_fp_2op_p_zds<0b0101, "fminnm", int_aarch64_sve_fminnm>;
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defm FMAX_ZPmZ : sve_fp_2op_p_zds<0b0110, "fmax", int_aarch64_sve_fmax>;
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defm FMIN_ZPmZ : sve_fp_2op_p_zds<0b0111, "fmin", int_aarch64_sve_fmin>;
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defm FABD_ZPmZ : sve_fp_2op_p_zds<0b1000, "fabd", int_aarch64_sve_fabd>;
|
||||
defm FADD_ZPmZ : sve_fp_2op_p_zds<0b0000, "fadd", "FADD_ZPZZ", int_aarch64_sve_fadd, DestructiveBinaryComm>;
|
||||
defm FSUB_ZPmZ : sve_fp_2op_p_zds<0b0001, "fsub", "FSUB_ZPZZ", int_aarch64_sve_fsub, DestructiveBinaryCommWithRev, "FSUBR_ZPmZ", 1>;
|
||||
defm FMUL_ZPmZ : sve_fp_2op_p_zds<0b0010, "fmul", "FMUL_ZPZZ", int_aarch64_sve_fmul, DestructiveBinaryComm>;
|
||||
defm FSUBR_ZPmZ : sve_fp_2op_p_zds<0b0011, "fsubr", "FSUBR_ZPZZ", int_aarch64_sve_fsubr, DestructiveBinaryCommWithRev, "FSUB_ZPmZ", 0>;
|
||||
defm FMAXNM_ZPmZ : sve_fp_2op_p_zds<0b0100, "fmaxnm", "FMAXNM_ZPZZ", int_aarch64_sve_fmaxnm, DestructiveBinaryComm>;
|
||||
defm FMINNM_ZPmZ : sve_fp_2op_p_zds<0b0101, "fminnm", "FMINNM_ZPZZ", int_aarch64_sve_fminnm, DestructiveBinaryComm>;
|
||||
defm FMAX_ZPmZ : sve_fp_2op_p_zds<0b0110, "fmax", "FMAX_ZPZZ", int_aarch64_sve_fmax, DestructiveBinaryComm>;
|
||||
defm FMIN_ZPmZ : sve_fp_2op_p_zds<0b0111, "fmin", "FMIN_ZPZZ", int_aarch64_sve_fmin, DestructiveBinaryComm>;
|
||||
defm FABD_ZPmZ : sve_fp_2op_p_zds<0b1000, "fabd", "FABD_ZPZZ", int_aarch64_sve_fabd, DestructiveBinaryComm>;
|
||||
defm FSCALE_ZPmZ : sve_fp_2op_p_zds_fscale<0b1001, "fscale", int_aarch64_sve_fscale>;
|
||||
defm FMULX_ZPmZ : sve_fp_2op_p_zds<0b1010, "fmulx", int_aarch64_sve_fmulx>;
|
||||
defm FDIVR_ZPmZ : sve_fp_2op_p_zds<0b1100, "fdivr", int_aarch64_sve_fdivr>;
|
||||
defm FDIV_ZPmZ : sve_fp_2op_p_zds<0b1101, "fdiv", int_aarch64_sve_fdiv>;
|
||||
defm FMULX_ZPmZ : sve_fp_2op_p_zds<0b1010, "fmulx", "FMULX_ZPZZ", int_aarch64_sve_fmulx, DestructiveBinaryComm>;
|
||||
defm FDIVR_ZPmZ : sve_fp_2op_p_zds<0b1100, "fdivr", "FDIVR_ZPZZ", int_aarch64_sve_fdivr, DestructiveBinaryCommWithRev, "FDIV_ZPmZ", 0>;
|
||||
defm FDIV_ZPmZ : sve_fp_2op_p_zds<0b1101, "fdiv", "FDIV_ZPZZ", int_aarch64_sve_fdiv, DestructiveBinaryCommWithRev, "FDIVR_ZPmZ", 1>;
|
||||
|
||||
defm FADD_ZPZZ : sve_fp_2op_p_zds_zx<int_aarch64_sve_fadd>;
|
||||
defm FSUB_ZPZZ : sve_fp_2op_p_zds_zx<int_aarch64_sve_fsub>;
|
||||
defm FMUL_ZPZZ : sve_fp_2op_p_zds_zx<int_aarch64_sve_fmul>;
|
||||
defm FSUBR_ZPZZ : sve_fp_2op_p_zds_zx<int_aarch64_sve_fsubr>;
|
||||
defm FMAXNM_ZPZZ : sve_fp_2op_p_zds_zx<int_aarch64_sve_fmaxnm>;
|
||||
defm FMINNM_ZPZZ : sve_fp_2op_p_zds_zx<int_aarch64_sve_fminnm>;
|
||||
defm FMAX_ZPZZ : sve_fp_2op_p_zds_zx<int_aarch64_sve_fmax>;
|
||||
defm FMIN_ZPZZ : sve_fp_2op_p_zds_zx<int_aarch64_sve_fmin>;
|
||||
defm FABD_ZPZZ : sve_fp_2op_p_zds_zx<int_aarch64_sve_fabd>;
|
||||
defm FMULX_ZPZZ : sve_fp_2op_p_zds_zx<int_aarch64_sve_fmulx>;
|
||||
defm FDIVR_ZPZZ : sve_fp_2op_p_zds_zx<int_aarch64_sve_fdivr>;
|
||||
defm FDIV_ZPZZ : sve_fp_2op_p_zds_zx<int_aarch64_sve_fdiv>;
|
||||
|
||||
defm FADD_ZZZ : sve_fp_3op_u_zd<0b000, "fadd", fadd>;
|
||||
defm FSUB_ZZZ : sve_fp_3op_u_zd<0b001, "fsub", fsub>;
|
||||
|
|
|
|||
|
|
@ -644,4 +644,7 @@ void AArch64PassConfig::addPreEmitPass() {
|
|||
if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
|
||||
TM->getTargetTriple().isOSBinFormatMachO())
|
||||
addPass(createAArch64CollectLOHPass());
|
||||
|
||||
// SVE bundles move prefixes with destructive operations.
|
||||
addPass(createUnpackMachineBundles(nullptr));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -367,8 +367,16 @@ class SVE_4_Op_Imm_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
|
|||
: Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3, (vt4 ImmTy:$Op4))),
|
||||
(inst $Op1, $Op2, $Op3, ImmTy:$Op4)>;
|
||||
|
||||
def SVEDup0 : ComplexPattern<i64, 0, "SelectDupZero", []>;
|
||||
def SVEDup0Undef : ComplexPattern<i64, 0, "SelectDupZeroOrUndef", []>;
|
||||
|
||||
let AddedComplexity = 1 in {
|
||||
class SVE_3_Op_Pat_SelZero<ValueType vtd, SDPatternOperator op, ValueType vt1,
|
||||
ValueType vt2, ValueType vt3, Instruction inst>
|
||||
: Pat<(vtd (vtd (op vt1:$Op1, (vselect vt1:$Op1, vt2:$Op2, (SVEDup0)), vt3:$Op3))),
|
||||
(inst $Op1, $Op2, $Op3)>;
|
||||
}
|
||||
|
||||
//
|
||||
// Common but less generic patterns.
|
||||
//
|
||||
|
|
@ -378,6 +386,55 @@ class SVE_1_Op_AllActive_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
|
|||
: Pat<(vtd (op vt1:$Op1)),
|
||||
(inst (IMPLICIT_DEF), (ptrue 31), $Op1)>;
|
||||
|
||||
//
|
||||
// Pseudo -> Instruction mappings
|
||||
//
|
||||
def getSVEPseudoMap : InstrMapping {
|
||||
let FilterClass = "SVEPseudo2Instr";
|
||||
let RowFields = ["PseudoName"];
|
||||
let ColFields = ["IsInstr"];
|
||||
let KeyCol = ["0"];
|
||||
let ValueCols = [["1"]];
|
||||
}
|
||||
|
||||
class SVEPseudo2Instr<string name, bit instr> {
|
||||
string PseudoName = name;
|
||||
bit IsInstr = instr;
|
||||
}
|
||||
|
||||
def getSVERevInstr : InstrMapping {
|
||||
let FilterClass = "SVEInstr2Rev";
|
||||
let RowFields = ["InstrName"];
|
||||
let ColFields = ["IsOrig"];
|
||||
let KeyCol = ["1"];
|
||||
let ValueCols = [["0"]];
|
||||
}
|
||||
|
||||
def getSVEOrigInstr : InstrMapping {
|
||||
let FilterClass = "SVEInstr2Rev";
|
||||
let RowFields = ["InstrName"];
|
||||
let ColFields = ["IsOrig"];
|
||||
let KeyCol = ["0"];
|
||||
let ValueCols = [["1"]];
|
||||
}
|
||||
|
||||
class SVEInstr2Rev<string name, string revname, bit nameIsOrig> {
|
||||
string InstrName = !if(nameIsOrig, name, revname);
|
||||
bit IsOrig = nameIsOrig;
|
||||
}
|
||||
|
||||
//
|
||||
// Pseudos for destructive operands
|
||||
//
|
||||
let hasNoSchedulingInfo = 1 in {
|
||||
class PredTwoOpPseudo<string name, ZPRRegOp zprty,
|
||||
FalseLanesEnum flags = FalseLanesNone>
|
||||
: SVEPseudo2Instr<name, 0>,
|
||||
Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, zprty:$Zs2), []> {
|
||||
let FalseLanes = flags;
|
||||
}
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// SVE Predicate Misc Group
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -1427,11 +1484,17 @@ class sve_fp_2op_p_zds<bits<2> sz, bits<4> opc, string asm,
|
|||
let ElementSize = zprty.ElementSize;
|
||||
}
|
||||
|
||||
multiclass sve_fp_2op_p_zds<bits<4> opc, string asm,
|
||||
SDPatternOperator op> {
|
||||
def _H : sve_fp_2op_p_zds<0b01, opc, asm, ZPR16>;
|
||||
def _S : sve_fp_2op_p_zds<0b10, opc, asm, ZPR32>;
|
||||
def _D : sve_fp_2op_p_zds<0b11, opc, asm, ZPR64>;
|
||||
multiclass sve_fp_2op_p_zds<bits<4> opc, string asm, string Ps,
|
||||
SDPatternOperator op, DestructiveInstTypeEnum flags,
|
||||
string revname="", bit isOrig=0> {
|
||||
let DestructiveInstType = flags in {
|
||||
def _H : sve_fp_2op_p_zds<0b01, opc, asm, ZPR16>,
|
||||
SVEPseudo2Instr<Ps # _H, 1>, SVEInstr2Rev<NAME # _H, revname # _H, isOrig>;
|
||||
def _S : sve_fp_2op_p_zds<0b10, opc, asm, ZPR32>,
|
||||
SVEPseudo2Instr<Ps # _S, 1>, SVEInstr2Rev<NAME # _S, revname # _S, isOrig>;
|
||||
def _D : sve_fp_2op_p_zds<0b11, opc, asm, ZPR64>,
|
||||
SVEPseudo2Instr<Ps # _D, 1>, SVEInstr2Rev<NAME # _D, revname # _D, isOrig>;
|
||||
}
|
||||
|
||||
def : SVE_3_Op_Pat<nxv8f16, op, nxv8i1, nxv8f16, nxv8f16, !cast<Instruction>(NAME # _H)>;
|
||||
def : SVE_3_Op_Pat<nxv4f32, op, nxv4i1, nxv4f32, nxv4f32, !cast<Instruction>(NAME # _S)>;
|
||||
|
|
@ -1449,6 +1512,16 @@ multiclass sve_fp_2op_p_zds_fscale<bits<4> opc, string asm,
|
|||
def : SVE_3_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, nxv2i64, !cast<Instruction>(NAME # _D)>;
|
||||
}
|
||||
|
||||
multiclass sve_fp_2op_p_zds_zx<SDPatternOperator op> {
|
||||
def _ZERO_H : PredTwoOpPseudo<NAME # _H, ZPR16, FalseLanesZero>;
|
||||
def _ZERO_S : PredTwoOpPseudo<NAME # _S, ZPR32, FalseLanesZero>;
|
||||
def _ZERO_D : PredTwoOpPseudo<NAME # _D, ZPR64, FalseLanesZero>;
|
||||
|
||||
def : SVE_3_Op_Pat_SelZero<nxv8f16, op, nxv8i1, nxv8f16, nxv8f16, !cast<Pseudo>(NAME # _ZERO_H)>;
|
||||
def : SVE_3_Op_Pat_SelZero<nxv4f32, op, nxv4i1, nxv4f32, nxv4f32, !cast<Pseudo>(NAME # _ZERO_S)>;
|
||||
def : SVE_3_Op_Pat_SelZero<nxv2f64, op, nxv2i1, nxv2f64, nxv2f64, !cast<Pseudo>(NAME # _ZERO_D)>;
|
||||
}
|
||||
|
||||
class sve_fp_ftmad<bits<2> sz, string asm, ZPRRegOp zprty>
|
||||
: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, imm32_0_7:$imm3),
|
||||
asm, "\t$Zdn, $_Zdn, $Zm, $imm3",
|
||||
|
|
|
|||
|
|
@ -68,6 +68,7 @@
|
|||
; CHECK-NEXT: Implement the 'patchable-function' attribute
|
||||
; CHECK-NEXT: AArch64 Branch Targets
|
||||
; CHECK-NEXT: Branch relaxation pass
|
||||
; CHECK-NEXT: Unpack machine instruction bundles
|
||||
; CHECK-NEXT: Contiguously Lay Out Funclets
|
||||
; CHECK-NEXT: StackMap Liveness Analysis
|
||||
; CHECK-NEXT: Live DEBUG_VALUE analysis
|
||||
|
|
|
|||
|
|
@ -178,6 +178,7 @@
|
|||
; CHECK-NEXT: AArch64 Branch Targets
|
||||
; CHECK-NEXT: Branch relaxation pass
|
||||
; CHECK-NEXT: AArch64 Compress Jump Tables
|
||||
; CHECK-NEXT: Unpack machine instruction bundles
|
||||
; CHECK-NEXT: Contiguously Lay Out Funclets
|
||||
; CHECK-NEXT: StackMap Liveness Analysis
|
||||
; CHECK-NEXT: Live DEBUG_VALUE analysis
|
||||
|
|
|
|||
|
|
@ -0,0 +1,261 @@
|
|||
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=sve < %s | FileCheck %s
|
||||
|
||||
;
|
||||
; FADD
|
||||
;
|
||||
|
||||
define <vscale x 4 x float> @fadd_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
|
||||
; CHECK-LABEL: fadd_s:
|
||||
; CHECK: movprfx z0.s, p0/z, z0.s
|
||||
; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
|
||||
%out = call <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4f32(<vscale x 4 x i1> %pg,
|
||||
<vscale x 4 x float> %a_z,
|
||||
<vscale x 4 x float> %b)
|
||||
ret <vscale x 4 x float> %out
|
||||
}
|
||||
|
||||
define <vscale x 2 x double> @fadd_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
|
||||
; CHECK-LABEL: fadd_d:
|
||||
; CHECK: movprfx z0.d, p0/z, z0.d
|
||||
; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
|
||||
%out = call <vscale x 2 x double> @llvm.aarch64.sve.fadd.nxv2f64(<vscale x 2 x i1> %pg,
|
||||
<vscale x 2 x double> %a_z,
|
||||
<vscale x 2 x double> %b)
|
||||
ret <vscale x 2 x double> %out
|
||||
}
|
||||
|
||||
;
|
||||
; FMAX
|
||||
;
|
||||
|
||||
define <vscale x 4 x float> @fmax_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
|
||||
; CHECK-LABEL: fmax_s:
|
||||
; CHECK: movprfx z0.s, p0/z, z0.s
|
||||
; CHECK-NEXT: fmax z0.s, p0/m, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
|
||||
%out = call <vscale x 4 x float> @llvm.aarch64.sve.fmax.nxv4f32(<vscale x 4 x i1> %pg,
|
||||
<vscale x 4 x float> %a_z,
|
||||
<vscale x 4 x float> %b)
|
||||
ret <vscale x 4 x float> %out
|
||||
}
|
||||
|
||||
define <vscale x 2 x double> @fmax_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
|
||||
; CHECK-LABEL: fmax_d:
|
||||
; CHECK: movprfx z0.d, p0/z, z0.d
|
||||
; CHECK-NEXT: fmax z0.d, p0/m, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
|
||||
%out = call <vscale x 2 x double> @llvm.aarch64.sve.fmax.nxv2f64(<vscale x 2 x i1> %pg,
|
||||
<vscale x 2 x double> %a_z,
|
||||
<vscale x 2 x double> %b)
|
||||
ret <vscale x 2 x double> %out
|
||||
}
|
||||
|
||||
;
|
||||
; FMAXNM
|
||||
;
|
||||
|
||||
define <vscale x 4 x float> @fmaxnm_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
|
||||
; CHECK-LABEL: fmaxnm_s:
|
||||
; CHECK: movprfx z0.s, p0/z, z0.s
|
||||
; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
|
||||
%out = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1> %pg,
|
||||
<vscale x 4 x float> %a_z,
|
||||
<vscale x 4 x float> %b)
|
||||
ret <vscale x 4 x float> %out
|
||||
}
|
||||
|
||||
define <vscale x 2 x double> @fmaxnm_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
|
||||
; CHECK-LABEL: fmaxnm_d:
|
||||
; CHECK: movprfx z0.d, p0/z, z0.d
|
||||
; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
|
||||
%out = call <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1> %pg,
|
||||
<vscale x 2 x double> %a_z,
|
||||
<vscale x 2 x double> %b)
|
||||
ret <vscale x 2 x double> %out
|
||||
}
|
||||
|
||||
;
|
||||
; FMIN
|
||||
;
|
||||
|
||||
define <vscale x 4 x float> @fmin_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
|
||||
; CHECK-LABEL: fmin_s:
|
||||
; CHECK: movprfx z0.s, p0/z, z0.s
|
||||
; CHECK-NEXT: fmin z0.s, p0/m, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
|
||||
%out = call <vscale x 4 x float> @llvm.aarch64.sve.fmin.nxv4f32(<vscale x 4 x i1> %pg,
|
||||
<vscale x 4 x float> %a_z,
|
||||
<vscale x 4 x float> %b)
|
||||
ret <vscale x 4 x float> %out
|
||||
}
|
||||
|
||||
define <vscale x 2 x double> @fmin_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
|
||||
; CHECK-LABEL: fmin_d:
|
||||
; CHECK: movprfx z0.d, p0/z, z0.d
|
||||
; CHECK-NEXT: fmin z0.d, p0/m, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
|
||||
%out = call <vscale x 2 x double> @llvm.aarch64.sve.fmin.nxv2f64(<vscale x 2 x i1> %pg,
|
||||
<vscale x 2 x double> %a_z,
|
||||
<vscale x 2 x double> %b)
|
||||
ret <vscale x 2 x double> %out
|
||||
}
|
||||
|
||||
;
|
||||
; FMINNM
|
||||
;
|
||||
|
||||
define <vscale x 4 x float> @fminnm_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
|
||||
; CHECK-LABEL: fminnm_s:
|
||||
; CHECK: movprfx z0.s, p0/z, z0.s
|
||||
; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
|
||||
%out = call <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1> %pg,
|
||||
<vscale x 4 x float> %a_z,
|
||||
<vscale x 4 x float> %b)
|
||||
ret <vscale x 4 x float> %out
|
||||
}
|
||||
|
||||
define <vscale x 2 x double> @fminnm_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
|
||||
; CHECK-LABEL: fminnm_d:
|
||||
; CHECK: movprfx z0.d, p0/z, z0.d
|
||||
; CHECK-NEXT: fminnm z0.d, p0/m, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
|
||||
%out = call <vscale x 2 x double> @llvm.aarch64.sve.fminnm.nxv2f64(<vscale x 2 x i1> %pg,
|
||||
<vscale x 2 x double> %a_z,
|
||||
<vscale x 2 x double> %b)
|
||||
ret <vscale x 2 x double> %out
|
||||
}
|
||||
|
||||
;
|
||||
; FMUL
|
||||
;
|
||||
|
||||
define <vscale x 4 x float> @fmul_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
|
||||
; CHECK-LABEL: fmul_s:
|
||||
; CHECK: movprfx z0.s, p0/z, z0.s
|
||||
; CHECK-NEXT: fmul z0.s, p0/m, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
|
||||
%out = call <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4f32(<vscale x 4 x i1> %pg,
|
||||
<vscale x 4 x float> %a_z,
|
||||
<vscale x 4 x float> %b)
|
||||
ret <vscale x 4 x float> %out
|
||||
}
|
||||
|
||||
define <vscale x 2 x double> @fmul_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
|
||||
; CHECK-LABEL: fmul_d:
|
||||
; CHECK: movprfx z0.d, p0/z, z0.d
|
||||
; CHECK-NEXT: fmul z0.d, p0/m, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
|
||||
%out = call <vscale x 2 x double> @llvm.aarch64.sve.fmul.nxv2f64(<vscale x 2 x i1> %pg,
|
||||
<vscale x 2 x double> %a_z,
|
||||
<vscale x 2 x double> %b)
|
||||
ret <vscale x 2 x double> %out
|
||||
}
|
||||
|
||||
;
|
||||
; FSUB
|
||||
;
|
||||
|
||||
define <vscale x 4 x float> @fsub_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
|
||||
; CHECK-LABEL: fsub_s:
|
||||
; CHECK: movprfx z0.s, p0/z, z0.s
|
||||
; CHECK-NEXT: fsub z0.s, p0/m, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
|
||||
%out = call <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1> %pg,
|
||||
<vscale x 4 x float> %a_z,
|
||||
<vscale x 4 x float> %b)
|
||||
ret <vscale x 4 x float> %out
|
||||
}
|
||||
|
||||
define <vscale x 2 x double> @fsub_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
|
||||
; CHECK-LABEL: fsub_d:
|
||||
; CHECK: movprfx z0.d, p0/z, z0.d
|
||||
; CHECK-NEXT: fsub z0.d, p0/m, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
|
||||
%out = call <vscale x 2 x double> @llvm.aarch64.sve.fsub.nxv2f64(<vscale x 2 x i1> %pg,
|
||||
<vscale x 2 x double> %a_z,
|
||||
<vscale x 2 x double> %b)
|
||||
ret <vscale x 2 x double> %out
|
||||
}
|
||||
|
||||
;
|
||||
; FSUBR
|
||||
;
|
||||
|
||||
define <vscale x 4 x float> @fsubr_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
|
||||
; CHECK-LABEL: fsubr_s:
|
||||
; CHECK: movprfx z0.s, p0/z, z0.s
|
||||
; CHECK-NEXT: fsubr z0.s, p0/m, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
|
||||
%out = call <vscale x 4 x float> @llvm.aarch64.sve.fsubr.nxv4f32(<vscale x 4 x i1> %pg,
|
||||
<vscale x 4 x float> %a_z,
|
||||
<vscale x 4 x float> %b)
|
||||
ret <vscale x 4 x float> %out
|
||||
}
|
||||
|
||||
define <vscale x 2 x double> @fsubr_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
|
||||
; CHECK-LABEL: fsubr_d:
|
||||
; CHECK: movprfx z0.d, p0/z, z0.d
|
||||
; CHECK-NEXT: fsubr z0.d, p0/m, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
|
||||
%out = call <vscale x 2 x double> @llvm.aarch64.sve.fsubr.nxv2f64(<vscale x 2 x i1> %pg,
|
||||
<vscale x 2 x double> %a_z,
|
||||
<vscale x 2 x double> %b)
|
||||
ret <vscale x 2 x double> %out
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.aarch64.sve.fabd.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
|
||||
declare <vscale x 2 x double> @llvm.aarch64.sve.fabd.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
|
||||
|
||||
declare <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
|
||||
declare <vscale x 2 x double> @llvm.aarch64.sve.fadd.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
|
||||
|
||||
declare <vscale x 4 x float> @llvm.aarch64.sve.fdiv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
|
||||
declare <vscale x 2 x double> @llvm.aarch64.sve.fdiv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
|
||||
|
||||
declare <vscale x 4 x float> @llvm.aarch64.sve.fdivr.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
|
||||
declare <vscale x 2 x double> @llvm.aarch64.sve.fdivr.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
|
||||
|
||||
declare <vscale x 4 x float> @llvm.aarch64.sve.fmax.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
|
||||
declare <vscale x 2 x double> @llvm.aarch64.sve.fmax.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
|
||||
|
||||
declare <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
|
||||
declare <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
|
||||
|
||||
declare <vscale x 4 x float> @llvm.aarch64.sve.fmin.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
|
||||
declare <vscale x 2 x double> @llvm.aarch64.sve.fmin.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
|
||||
|
||||
declare <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
|
||||
declare <vscale x 2 x double> @llvm.aarch64.sve.fminnm.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
|
||||
|
||||
declare <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
|
||||
declare <vscale x 2 x double> @llvm.aarch64.sve.fmul.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
|
||||
|
||||
declare <vscale x 4 x float> @llvm.aarch64.sve.fmulx.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
|
||||
declare <vscale x 2 x double> @llvm.aarch64.sve.fmulx.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
|
||||
|
||||
declare <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
|
||||
declare <vscale x 2 x double> @llvm.aarch64.sve.fsub.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
|
||||
|
||||
declare <vscale x 4 x float> @llvm.aarch64.sve.fsubr.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
|
||||
declare <vscale x 2 x double> @llvm.aarch64.sve.fsubr.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
|
||||
Loading…
Reference in New Issue