From a599e1320c52ef8c429001da197e84c0485e9df8 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@intel.com>
Date: Sat, 8 Aug 2020 12:50:33 -0700
Subject: [PATCH] [X86] Add VPTERNLOG test cases where the root node will be
 X86ISD::ANDNP. NFC

We currently fail to match this.
---
 llvm/test/CodeGen/X86/avx512vl-logic.ll | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/llvm/test/CodeGen/X86/avx512vl-logic.ll b/llvm/test/CodeGen/X86/avx512vl-logic.ll
index 13c4c8afb9a8..9bd0b053436a 100644
--- a/llvm/test/CodeGen/X86/avx512vl-logic.ll
+++ b/llvm/test/CodeGen/X86/avx512vl-logic.ll
@@ -1297,3 +1297,27 @@ define <4 x i64> @ternlog_masky_xor_and_mask_ymm(<4 x i64> %x, <4 x i64> %y, <4
   %c = select <4 x i1> %m, <4 x i64> %b, <4 x i64> %y
   ret <4 x i64> %c
 }
+
+define <4 x i32> @ternlog_andn_or(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
+; CHECK-LABEL: ternlog_andn_or:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    vorps %xmm2, %xmm1, %xmm1
+; CHECK-NEXT:    vandnps %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %a = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %b = or <4 x i32> %y, %z
+  %c = and <4 x i32> %a, %b
+  ret <4 x i32> %c
+}
+
+define <4 x i32> @ternlog_andn_or_2(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
+; CHECK-LABEL: ternlog_andn_or_2:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    vorps %xmm2, %xmm1, %xmm1
+; CHECK-NEXT:    vandnps %xmm0, %xmm1, %xmm0
+; CHECK-NEXT:    retq
+  %a = or <4 x i32> %y, %z
+  %b = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %c = and <4 x i32> %x, %b
+  ret <4 x i32> %c
+}