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[X86] Use __builtin_ia32_paddq and __builtin_ia32_psubq to implement a couple intrinsics that were supposed to operate on MMX registers. Otherwise we end up operating on GPRs. Throw in a test for _mm_mul_su32 while I was there. 

llvm-svn: 252711
This commit is contained in:
Craig Topper 2015-11-11 08:00:41 +00:00
parent 880f60b7b3
commit a5455524c2
2 changed files with 20 additions and 2 deletions
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4
clang/lib/Headers/emmintrin.h
View File

@ -647,7 +647,7 @@ _mm_add_epi32(__m128i __a, __m128i __b)
static __inline__ __m64 __DEFAULT_FN_ATTRS
_mm_add_si64(__m64 __a, __m64 __b)
{
return __a + __b;
return (__m64)__builtin_ia32_paddq(__a, __b);
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
@ -779,7 +779,7 @@ _mm_sub_epi32(__m128i __a, __m128i __b)
static __inline__ __m64 __DEFAULT_FN_ATTRS
_mm_sub_si64(__m64 __a, __m64 __b)
{
return __a - __b;
return (__m64)__builtin_ia32_psubq(__a, __b);
}
static __inline__ __m128i __DEFAULT_FN_ATTRS

18
clang/test/CodeGen/sse-builtins.c
View File

@ -495,3 +495,21 @@ __m128i test_mm_undefined_si128() {
// CHECK: ret <2 x i64> undef
return _mm_undefined_si128();
}
__m64 test_mm_add_si64(__m64 __a, __m64 __b) {
// CHECK-LABEL: @test_mm_add_si64
// CHECK @llvm.x86.mmx.padd.q(x86_mmx %{{.*}}, x86_mmx %{{.*}})
return _mm_add_si64(__a, __b);
}
__m64 test_mm_sub_si64(__m64 __a, __m64 __b) {
// CHECK-LABEL: @test_mm_sub_si64
// CHECK @llvm.x86.mmx.psub.q(x86_mmx %{{.*}}, x86_mmx %{{.*}})
return _mm_sub_si64(__a, __b);
}
__m64 test_mm_mul_su32(__m64 __a, __m64 __b) {
// CHECK-LABEL: @test_mm_mul_su32
// CHECK @llvm.x86.mmx.pmulu.dq(x86_mmx %{{.*}}, x86_mmx %{{.*}})
return _mm_mul_su32(__a, __b);
}