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[AArch64] Fix encoding for lsl #12 in add/sub immediates 

Whenever an add/sub immediate needs a fixup, we set that immediate field to zero,
which is correct, but we also set the shift bits to zero, which is not true for
instructions that use lsl #12. This patch makes sure that if lsl #12 was used,
it will appear in the encoding of the instruction.

Differential Revision: https://reviews.llvm.org/D23930

llvm-svn: 281898
This commit is contained in:
Diana Picus 2016-09-19 11:10:18 +00:00
parent 122d6d74f6
commit a53660e4a3
4 changed files with 27 additions and 12 deletions
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4
llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
View File

@ -253,7 +253,7 @@ AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
assert((ShiftVal == 0 || ShiftVal == 12) && assert((ShiftVal == 0 || ShiftVal == 12) &&
"unexpected shift value for add/sub immediate"); "unexpected shift value for add/sub immediate");
if (MO.isImm()) if (MO.isImm())
return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << 12)); return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << ShiftVal));
assert(MO.isExpr() && "Unable to encode MCOperand!"); assert(MO.isExpr() && "Unable to encode MCOperand!");
const MCExpr *Expr = MO.getExpr(); const MCExpr *Expr = MO.getExpr();
@ -263,7 +263,7 @@ AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
++MCNumFixups; ++MCNumFixups;
return 0; return ShiftVal == 0 ? 0 : (1 << ShiftVal);
} }
/// getCondBranchTargetOpValue - Return the encoded value for a conditional /// getCondBranchTargetOpValue - Return the encoded value for a conditional

12
llvm/test/MC/AArch64/darwin-reloc-addsubimm.s Normal file
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@ -0,0 +1,12 @@
// RUN: llvm-mc -triple=aarch64-darwin -filetype=obj %s -o - | \
// RUN: llvm-objdump -r -d - | FileCheck -check-prefix=OBJ %s
// OBJ-LABEL: Disassembly of section __TEXT,__text:
add x2, x3, _data@pageoff
// OBJ: [[addr:[0-9a-f]+]]: 62 00 00 91 add x2, x3, #0
// OBJ-NEXT: [[addr]]: ARM64_RELOC_PAGEOFF12 _data
add x2, x3, #_data@pageoff, lsl #12
// OBJ: [[addr:[0-9a-f]+]]: 62 00 40 91 add x2, x3, #0, lsl #12
// OBJ-NEXT: [[addr]]: ARM64_RELOC_PAGEOFF12 _data

15
llvm/test/MC/AArch64/elf-reloc-addsubimm.s
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@ -1,10 +1,13 @@
// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \ // RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \
// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s // RUN: llvm-objdump -r -d - | FileCheck -check-prefix=OBJ %s
// OBJ-LABEL: Disassembly of section .text:
add x2, x3, #:lo12:some_label add x2, x3, #:lo12:some_label
// OBJ: [[addr:[0-9a-f]+]]: 62 00 00 91 add x2, x3, #0
// OBJ-NEXT: [[addr]]: R_AARCH64_ADD_ABS_LO12_NC some_label
add x2, x3, #:lo12:some_label, lsl #12
// OBJ: [[addr:[0-9a-f]+]]: 62 00 40 91 add x2, x3, #0, lsl #12
// OBJ-NEXT: [[addr]]: R_AARCH64_ADD_ABS_LO12_NC some_label
// OBJ: Relocations [
// OBJ-NEXT: Section {{.*}} .rela.text {
// OBJ-NEXT: 0x0 R_AARCH64_ADD_ABS_LO12_NC some_label 0x0
// OBJ-NEXT: }
// OBJ-NEXT: ]

8
llvm/test/MC/AArch64/tls-relocs.s
View File

@ -92,9 +92,9 @@
add x17, x18, #:dtprel_hi12:var, lsl #12 add x17, x18, #:dtprel_hi12:var, lsl #12
add w19, w20, #:dtprel_hi12:var, lsl #12 add w19, w20, #:dtprel_hi12:var, lsl #12
// CHECK: add x17, x18, :dtprel_hi12:var, lsl #12 // encoding: [0x51,0bAAAAAA10,0b00AAAAAA,0x91] // CHECK: add x17, x18, :dtprel_hi12:var, lsl #12 // encoding: [0x51,0bAAAAAA10,0b01AAAAAA,0x91]
// CHECK: // fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_aarch64_add_imm12 // CHECK: // fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_aarch64_add_imm12
// CHECK: add w19, w20, :dtprel_hi12:var, lsl #12 // encoding: [0x93,0bAAAAAA10,0b00AAAAAA,0x11] // CHECK: add w19, w20, :dtprel_hi12:var, lsl #12 // encoding: [0x93,0bAAAAAA10,0b01AAAAAA,0x11]
// CHECK: // fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_aarch64_add_imm12 // CHECK: // fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_aarch64_add_imm12
// CHECK-ELF-NEXT: 0x40 R_AARCH64_TLSLD_ADD_DTPREL_HI12 [[VARSYM]] // CHECK-ELF-NEXT: 0x40 R_AARCH64_TLSLD_ADD_DTPREL_HI12 [[VARSYM]]
@ -294,9 +294,9 @@
add x17, x18, #:tprel_hi12:var, lsl #12 add x17, x18, #:tprel_hi12:var, lsl #12
add w19, w20, #:tprel_hi12:var, lsl #12 add w19, w20, #:tprel_hi12:var, lsl #12
// CHECK: add x17, x18, :tprel_hi12:var, lsl #12 // encoding: [0x51,0bAAAAAA10,0b00AAAAAA,0x91] // CHECK: add x17, x18, :tprel_hi12:var, lsl #12 // encoding: [0x51,0bAAAAAA10,0b01AAAAAA,0x91]
// CHECK: // fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_aarch64_add_imm12 // CHECK: // fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_aarch64_add_imm12
// CHECK: add w19, w20, :tprel_hi12:var, lsl #12 // encoding: [0x93,0bAAAAAA10,0b00AAAAAA,0x11] // CHECK: add w19, w20, :tprel_hi12:var, lsl #12 // encoding: [0x93,0bAAAAAA10,0b01AAAAAA,0x11]
// CHECK: // fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_aarch64_add_imm12 // CHECK: // fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_aarch64_add_imm12
// CHECK-ELF-NEXT: 0xCC R_AARCH64_TLSLE_ADD_TPREL_HI12 [[VARSYM]] // CHECK-ELF-NEXT: 0xCC R_AARCH64_TLSLE_ADD_TPREL_HI12 [[VARSYM]]