From a53349251c4469b4c162a6ea096425b309c7ecff Mon Sep 17 00:00:00 2001
From: Clement Courbet <courbet@google.com>
Date: Mon, 2 Jul 2018 06:39:55 +0000
Subject: [PATCH] [llvm-exegesis][NFC] Cleanup useless braces.

llvm-svn: 336076
---
 llvm/tools/llvm-exegesis/lib/X86/Target.cpp | 24 +++++++--------------
 1 file changed, 8 insertions(+), 16 deletions(-)

diff --git a/llvm/tools/llvm-exegesis/lib/X86/Target.cpp b/llvm/tools/llvm-exegesis/lib/X86/Target.cpp
index 8b878e503dee..594c48bbdba9 100644
--- a/llvm/tools/llvm-exegesis/lib/X86/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/X86/Target.cpp
@@ -132,32 +132,24 @@ class ExegesisX86Target : public ExegesisTarget {
 
   std::vector<llvm::MCInst>
   setRegToConstant(unsigned Reg) const override {
-    if (llvm::X86::GR8RegClass.contains(Reg)) {
+    if (llvm::X86::GR8RegClass.contains(Reg))
       return {llvm::MCInstBuilder(llvm::X86::MOV8ri).addReg(Reg).addImm(1)};
-    }
-    if (llvm::X86::GR16RegClass.contains(Reg)) {
+    if (llvm::X86::GR16RegClass.contains(Reg))
       return {llvm::MCInstBuilder(llvm::X86::MOV16ri).addReg(Reg).addImm(1)};
-    }
-    if (llvm::X86::GR32RegClass.contains(Reg)) {
+    if (llvm::X86::GR32RegClass.contains(Reg))
       return {llvm::MCInstBuilder(llvm::X86::MOV32ri).addReg(Reg).addImm(1)};
-    }
-    if (llvm::X86::GR64RegClass.contains(Reg)) {
+    if (llvm::X86::GR64RegClass.contains(Reg))
       return {llvm::MCInstBuilder(llvm::X86::MOV64ri32).addReg(Reg).addImm(1)};
-    }
-    if (llvm::X86::VR128XRegClass.contains(Reg)) {
+    if (llvm::X86::VR128XRegClass.contains(Reg))
       return setVectorRegToConstant(Reg, 16, llvm::X86::VMOVDQUrm);
-    }
-    if (llvm::X86::VR256XRegClass.contains(Reg)) {
+    if (llvm::X86::VR256XRegClass.contains(Reg))
       return setVectorRegToConstant(Reg, 32, llvm::X86::VMOVDQUYrm);
-    }
-    if (llvm::X86::VR512RegClass.contains(Reg)) {
+    if (llvm::X86::VR512RegClass.contains(Reg))
       return setVectorRegToConstant(Reg, 64, llvm::X86::VMOVDQU64Zrm);
-    }
     if (llvm::X86::RFP32RegClass.contains(Reg) ||
         llvm::X86::RFP64RegClass.contains(Reg) ||
-        llvm::X86::RFP80RegClass.contains(Reg)) {
+        llvm::X86::RFP80RegClass.contains(Reg))
       return setVectorRegToConstant(Reg, 8, llvm::X86::LD_Fp64m);
-    }
     return {};
   }