forked from OSchip/llvm-project
[AArch64][GlobalISel] Add a post-legalize combine for lowering vector-immediate G_ASHR/G_LSHR.
In order to select the immediate forms using the imported patterns, we need to lower them into new G_VASHR/G_VLSHR target generic ops. Add a combine to do this matching build_vector of constant operands. With this, we get selection for free.
This commit is contained in:
Amara Emerson
parent
3a799deed7
commit
a513fdec90
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@ -75,11 +75,20 @@ def ext: GICombineRule <
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// instruction.
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def shuffle_vector_pseudos : GICombineGroup<[dup, rev, ext, zip, uzp, trn]>;
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def vashr_vlshr_imm_matchdata : GIDefMatchData<"int64_t">;
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def vashr_vlshr_imm : GICombineRule<
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(defs root:$root, vashr_vlshr_imm_matchdata:$matchinfo),
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(match (wip_match_opcode G_ASHR, G_LSHR):$root,
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[{ return matchVAshrLshrImm(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyVAshrLshrImm(*${root}, MRI, ${matchinfo}); }])
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>;
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def AArch64PostLegalizerCombinerHelper
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: GICombinerHelper<"AArch64GenPostLegalizerCombinerHelper",
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[copy_prop, erase_undef_store, combines_for_extload,
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sext_trunc_sextload, shuffle_vector_pseudos,
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hoist_logic_op_with_same_opcode_hands,
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and_trivial_mask]> {
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and_trivial_mask, vashr_vlshr_imm]> {
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let DisableRuleOption = "aarch64postlegalizercombiner-disable-rule";
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}
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@ -111,6 +111,18 @@ def G_EXT: AArch64GenericInstruction {
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let InOperandList = (ins type0:$v1, type0:$v2, untyped_imm_0:$imm);
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}
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// Represents a vector G_ASHR with an immediate.
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def G_VASHR : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src1, untyped_imm_0:$imm);
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}
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// Represents a vector G_LSHR with an immediate.
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def G_VLSHR : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src1, untyped_imm_0:$imm);
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}
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def : GINodeEquiv<G_REV16, AArch64rev16>;
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def : GINodeEquiv<G_REV32, AArch64rev32>;
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def : GINodeEquiv<G_REV64, AArch64rev64>;
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@ -122,3 +134,5 @@ def : GINodeEquiv<G_DUP, AArch64dup>;
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def : GINodeEquiv<G_TRN1, AArch64trn1>;
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def : GINodeEquiv<G_TRN2, AArch64trn2>;
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def : GINodeEquiv<G_EXT, AArch64ext>;
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def : GINodeEquiv<G_VASHR, AArch64vashr>;
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def : GINodeEquiv<G_VLSHR, AArch64vlshr>;
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@ -15,14 +15,19 @@
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//===----------------------------------------------------------------------===//
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#include "AArch64TargetMachine.h"
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
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#include "llvm/CodeGen/GlobalISel/Combiner.h"
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#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
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#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
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#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
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#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/Support/Debug.h"
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@ -368,6 +373,45 @@ static bool applyEXT(MachineInstr &MI, ShuffleVectorPseudo &MatchInfo) {
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return true;
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}
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/// isVShiftRImm - Check if this is a valid vector for the immediate
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/// operand of a vector shift right operation. The value must be in the range:
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/// 1 <= Value <= ElementBits for a right shift.
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static bool isVShiftRImm(Register Reg, MachineRegisterInfo &MRI, LLT Ty,
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int64_t &Cnt) {
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assert(Ty.isVector() && "vector shift count is not a vector type");
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MachineInstr *MI = MRI.getVRegDef(Reg);
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auto Cst = getBuildVectorConstantSplat(*MI, MRI);
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if (!Cst)
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return false;
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Cnt = *Cst;
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int64_t ElementBits = Ty.getScalarSizeInBits();
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return Cnt >= 1 && Cnt <= ElementBits;
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}
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/// Match a vector G_ASHR or G_LSHR with a valid immediate shift.
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static bool matchVAshrLshrImm(MachineInstr &MI, MachineRegisterInfo &MRI,
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int64_t &Imm) {
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assert(MI.getOpcode() == TargetOpcode::G_ASHR ||
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MI.getOpcode() == TargetOpcode::G_LSHR);
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LLT Ty = MRI.getType(MI.getOperand(1).getReg());
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if (!Ty.isVector())
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return false;
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return isVShiftRImm(MI.getOperand(2).getReg(), MRI, Ty, Imm);
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}
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static bool applyVAshrLshrImm(MachineInstr &MI, MachineRegisterInfo &MRI,
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int64_t &Imm) {
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unsigned Opc = MI.getOpcode();
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assert(Opc == TargetOpcode::G_ASHR || Opc == TargetOpcode::G_LSHR);
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unsigned NewOpc =
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Opc == TargetOpcode::G_ASHR ? AArch64::G_VASHR : AArch64::G_VLSHR;
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MachineIRBuilder MIB(MI);
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auto ImmDef = MIB.buildConstant(LLT::scalar(32), Imm);
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MIB.buildInstr(NewOpc, {MI.getOperand(0)}, {MI.getOperand(1), ImmDef});
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MI.eraseFromParent();
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return true;
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}
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#define AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
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#include "AArch64GenPostLegalizeGICombiner.inc"
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#undef AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
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@ -0,0 +1,147 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
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...
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---
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name: ashr_v4s32
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d0, $d1
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; CHECK-LABEL: name: ashr_v4s32
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
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; CHECK: [[VASHR:%[0-9]+]]:_(<4 x s32>) = G_VASHR [[COPY]], [[C]](s32)
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; CHECK: $q0 = COPY [[VASHR]](<4 x s32>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<4 x s32>) = COPY $q0
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%1:_(s32) = G_CONSTANT i32 5
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%2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)
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%3:_(<4 x s32>) = G_ASHR %0, %2(<4 x s32>)
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$q0 = COPY %3(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: lshr_v4s32
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d0, $d1
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; CHECK-LABEL: name: lshr_v4s32
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
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; CHECK: [[VLSHR:%[0-9]+]]:_(<4 x s32>) = G_VLSHR [[COPY]], [[C]](s32)
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; CHECK: $q0 = COPY [[VLSHR]](<4 x s32>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<4 x s32>) = COPY $q0
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%1:_(s32) = G_CONSTANT i32 5
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%2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)
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%3:_(<4 x s32>) = G_LSHR %0, %2(<4 x s32>)
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$q0 = COPY %3(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: lshr_v8s16
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d0, $d1
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; CHECK-LABEL: name: lshr_v8s16
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
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; CHECK: [[VLSHR:%[0-9]+]]:_(<8 x s16>) = G_VLSHR [[COPY]], [[C]](s32)
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; CHECK: $q0 = COPY [[VLSHR]](<8 x s16>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<8 x s16>) = COPY $q0
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%1:_(s16) = G_CONSTANT i16 5
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%2:_(<8 x s16>) = G_BUILD_VECTOR %1(s16), %1(s16), %1(s16), %1(s16), %1(s16), %1(s16), %1(s16), %1(s16)
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%3:_(<8 x s16>) = G_LSHR %0, %2(<8 x s16>)
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$q0 = COPY %3(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: imm_too_large
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d0, $d1
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; CHECK-LABEL: name: imm_too_large
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 40
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
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; CHECK: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[COPY]], [[BUILD_VECTOR]](<4 x s32>)
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; CHECK: $q0 = COPY [[LSHR]](<4 x s32>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<4 x s32>) = COPY $q0
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%1:_(s32) = G_CONSTANT i32 40
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%2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)
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%3:_(<4 x s32>) = G_LSHR %0, %2(<4 x s32>)
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$q0 = COPY %3(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: imm_zero
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d0, $d1
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; CHECK-LABEL: name: imm_zero
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
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; CHECK: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[COPY]], [[BUILD_VECTOR]](<4 x s32>)
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; CHECK: $q0 = COPY [[LSHR]](<4 x s32>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<4 x s32>) = COPY $q0
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%1:_(s32) = G_CONSTANT i32 0
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%2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)
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%3:_(<4 x s32>) = G_LSHR %0, %2(<4 x s32>)
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$q0 = COPY %3(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: imm_not_splat
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d0, $d1
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; CHECK-LABEL: name: imm_not_splat
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C]](s32), [[C]](s32)
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; CHECK: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[COPY]], [[BUILD_VECTOR]](<4 x s32>)
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; CHECK: $q0 = COPY [[LSHR]](<4 x s32>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<4 x s32>) = COPY $q0
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%1:_(s32) = G_CONSTANT i32 4
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%4:_(s32) = G_CONSTANT i32 6
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%2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %4(s32), %1(s32), %1(s32)
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%3:_(<4 x s32>) = G_LSHR %0, %2(<4 x s32>)
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$q0 = COPY %3(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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@ -372,3 +372,43 @@ body: |
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$d0 = COPY %2(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: vashr_v4i16_imm
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $d0, $d1
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; CHECK-LABEL: name: vashr_v4i16_imm
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[SSHRv4i16_shift:%[0-9]+]]:fpr64 = SSHRv4i16_shift [[COPY]], 5
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; CHECK: $d0 = COPY [[SSHRv4i16_shift]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<4 x s16>) = COPY $d0
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%1:gpr(s32) = G_CONSTANT i32 5
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%2:fpr(<4 x s16>) = G_VASHR %0, %1
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$d0 = COPY %2(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: vlshr_v4i16_imm
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $d0, $d1
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; CHECK-LABEL: name: vlshr_v4i16_imm
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[USHRv4i16_shift:%[0-9]+]]:fpr64 = USHRv4i16_shift [[COPY]], 5
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; CHECK: $d0 = COPY [[USHRv4i16_shift]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<4 x s16>) = COPY $d0
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%1:gpr(s32) = G_CONSTANT i32 5
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%2:fpr(<4 x s16>) = G_VLSHR %0, %1
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$d0 = COPY %2(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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