forked from OSchip/llvm-project
[AArch64][Falkor] Fix correctness bug in falkor prefetcher fix pass and correct some opcode tag computations.
Summary: This addresses a correctness bug for LD[1234]*_POST opcodes that have the prefetcher fix applied to them: the base register was not being written back from the temp after being incremented, so it would appear to never be incremented. Also, fix some opcode tag computations based on some updated HW details to get better tag avoidance and thus better prefetcher performance. Reviewers: mcrosier Subscribers: aemerson, rengolin, javed.absar, kristof.beyls Differential Revision: https://reviews.llvm.org/D38256 llvm-svn: 314251
This commit is contained in:
Geoff Berry
parent
b7e4c94c6c
commit
a4b2f5df5e
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@ -240,27 +240,27 @@ static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
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default:
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return None;
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case AArch64::LD1i8:
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case AArch64::LD1i16:
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case AArch64::LD1i32:
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case AArch64::LD1i64:
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case AArch64::LD2i8:
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case AArch64::LD2i16:
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case AArch64::LD2i32:
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case AArch64::LD2i64:
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case AArch64::LD3i8:
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case AArch64::LD3i16:
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case AArch64::LD3i32:
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case AArch64::LD4i8:
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case AArch64::LD4i16:
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case AArch64::LD4i32:
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DestRegIdx = 0;
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BaseRegIdx = 3;
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OffsetIdx = -1;
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IsPrePost = false;
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break;
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case AArch64::LD1i8:
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case AArch64::LD1i16:
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case AArch64::LD1i32:
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case AArch64::LD2i8:
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case AArch64::LD2i16:
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case AArch64::LD2i32:
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case AArch64::LD3i8:
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case AArch64::LD3i16:
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case AArch64::LD3i32:
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case AArch64::LD3i64:
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case AArch64::LD4i8:
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case AArch64::LD4i16:
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case AArch64::LD4i32:
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case AArch64::LD4i64:
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DestRegIdx = -1;
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BaseRegIdx = 3;
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@ -284,23 +284,16 @@ static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
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case AArch64::LD1Rv4s:
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case AArch64::LD1Rv8h:
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case AArch64::LD1Rv16b:
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case AArch64::LD1Twov1d:
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case AArch64::LD1Twov2s:
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case AArch64::LD1Twov4h:
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case AArch64::LD1Twov8b:
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case AArch64::LD2Twov2s:
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case AArch64::LD2Twov4s:
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case AArch64::LD2Twov8b:
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case AArch64::LD2Rv1d:
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case AArch64::LD2Rv2s:
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case AArch64::LD2Rv4s:
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case AArch64::LD2Rv8b:
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DestRegIdx = 0;
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BaseRegIdx = 1;
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OffsetIdx = -1;
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IsPrePost = false;
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break;
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case AArch64::LD1Twov1d:
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case AArch64::LD1Twov2s:
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case AArch64::LD1Twov4h:
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case AArch64::LD1Twov8b:
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case AArch64::LD1Twov2d:
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case AArch64::LD1Twov4s:
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case AArch64::LD1Twov8h:
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@ -321,10 +314,17 @@ static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
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case AArch64::LD1Fourv4s:
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case AArch64::LD1Fourv8h:
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case AArch64::LD1Fourv16b:
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case AArch64::LD2Twov2s:
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case AArch64::LD2Twov4s:
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case AArch64::LD2Twov8b:
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case AArch64::LD2Twov2d:
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case AArch64::LD2Twov4h:
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case AArch64::LD2Twov8h:
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case AArch64::LD2Twov16b:
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case AArch64::LD2Rv1d:
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case AArch64::LD2Rv2s:
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case AArch64::LD2Rv4s:
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case AArch64::LD2Rv8b:
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case AArch64::LD2Rv2d:
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case AArch64::LD2Rv4h:
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case AArch64::LD2Rv8h:
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@ -365,32 +365,32 @@ static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
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IsPrePost = false;
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break;
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case AArch64::LD1i8_POST:
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case AArch64::LD1i16_POST:
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case AArch64::LD1i32_POST:
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case AArch64::LD1i64_POST:
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case AArch64::LD2i8_POST:
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case AArch64::LD2i16_POST:
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case AArch64::LD2i32_POST:
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case AArch64::LD2i64_POST:
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case AArch64::LD3i8_POST:
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case AArch64::LD3i16_POST:
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case AArch64::LD3i32_POST:
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case AArch64::LD4i8_POST:
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case AArch64::LD4i16_POST:
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case AArch64::LD4i32_POST:
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DestRegIdx = 1;
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BaseRegIdx = 4;
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OffsetIdx = 5;
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IsPrePost = false;
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IsPrePost = true;
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break;
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case AArch64::LD1i8_POST:
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case AArch64::LD1i16_POST:
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case AArch64::LD1i32_POST:
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case AArch64::LD2i8_POST:
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case AArch64::LD2i16_POST:
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case AArch64::LD2i32_POST:
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case AArch64::LD3i8_POST:
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case AArch64::LD3i16_POST:
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case AArch64::LD3i32_POST:
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case AArch64::LD3i64_POST:
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case AArch64::LD4i8_POST:
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case AArch64::LD4i16_POST:
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case AArch64::LD4i32_POST:
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case AArch64::LD4i64_POST:
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DestRegIdx = -1;
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BaseRegIdx = 4;
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OffsetIdx = 5;
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IsPrePost = false;
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IsPrePost = true;
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break;
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case AArch64::LD1Onev1d_POST:
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@ -409,23 +409,16 @@ static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
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case AArch64::LD1Rv4s_POST:
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case AArch64::LD1Rv8h_POST:
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case AArch64::LD1Rv16b_POST:
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DestRegIdx = 1;
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BaseRegIdx = 2;
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OffsetIdx = 3;
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IsPrePost = true;
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break;
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case AArch64::LD1Twov1d_POST:
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case AArch64::LD1Twov2s_POST:
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case AArch64::LD1Twov4h_POST:
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case AArch64::LD1Twov8b_POST:
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case AArch64::LD2Twov2s_POST:
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case AArch64::LD2Twov4s_POST:
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case AArch64::LD2Twov8b_POST:
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case AArch64::LD2Rv1d_POST:
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case AArch64::LD2Rv2s_POST:
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case AArch64::LD2Rv4s_POST:
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case AArch64::LD2Rv8b_POST:
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DestRegIdx = 1;
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BaseRegIdx = 2;
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OffsetIdx = 3;
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IsPrePost = false;
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break;
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case AArch64::LD1Twov2d_POST:
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case AArch64::LD1Twov4s_POST:
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case AArch64::LD1Twov8h_POST:
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@ -446,10 +439,17 @@ static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
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case AArch64::LD1Fourv4s_POST:
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case AArch64::LD1Fourv8h_POST:
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case AArch64::LD1Fourv16b_POST:
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case AArch64::LD2Twov2s_POST:
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case AArch64::LD2Twov4s_POST:
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case AArch64::LD2Twov8b_POST:
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case AArch64::LD2Twov2d_POST:
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case AArch64::LD2Twov4h_POST:
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case AArch64::LD2Twov8h_POST:
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case AArch64::LD2Twov16b_POST:
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case AArch64::LD2Rv1d_POST:
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case AArch64::LD2Rv2s_POST:
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case AArch64::LD2Rv4s_POST:
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case AArch64::LD2Rv8b_POST:
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case AArch64::LD2Rv2d_POST:
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case AArch64::LD2Rv4h_POST:
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case AArch64::LD2Rv8h_POST:
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@ -487,7 +487,7 @@ static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
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DestRegIdx = -1;
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BaseRegIdx = 2;
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OffsetIdx = 3;
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IsPrePost = false;
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IsPrePost = true;
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break;
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case AArch64::LDRBBroW:
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@ -592,16 +592,19 @@ static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
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IsPrePost = true;
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break;
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case AArch64::LDNPDi:
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case AArch64::LDNPQi:
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case AArch64::LDNPSi:
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case AArch64::LDPQi:
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case AArch64::LDPDi:
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case AArch64::LDPSi:
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DestRegIdx = -1;
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BaseRegIdx = 2;
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OffsetIdx = 3;
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IsPrePost = false;
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break;
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case AArch64::LDPDi:
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case AArch64::LDPSWi:
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case AArch64::LDPSi:
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case AArch64::LDPWi:
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case AArch64::LDPXi:
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DestRegIdx = 0;
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@ -612,18 +615,18 @@ static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
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case AArch64::LDPQpost:
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case AArch64::LDPQpre:
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case AArch64::LDPDpost:
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case AArch64::LDPDpre:
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case AArch64::LDPSpost:
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case AArch64::LDPSpre:
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DestRegIdx = -1;
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BaseRegIdx = 3;
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OffsetIdx = 4;
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IsPrePost = true;
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break;
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case AArch64::LDPDpost:
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case AArch64::LDPDpre:
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case AArch64::LDPSWpost:
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case AArch64::LDPSWpre:
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case AArch64::LDPSpost:
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case AArch64::LDPSpre:
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case AArch64::LDPWpost:
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case AArch64::LDPWpre:
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case AArch64::LDPXpost:
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@ -1,12 +1,7 @@
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# RUN: llc -mtriple=aarch64-linux-gnu -mcpu=falkor -run-pass falkor-hwpf-fix-late -o - %s | FileCheck %s
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--- |
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@g = external global i32
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define void @hwpf1() { ret void }
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define void @hwpf2() { ret void }
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...
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---
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# Verify that the tag collision between the loads is resolved.
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# Verify that the tag collision between the loads is resolved for various load opcodes.
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# CHECK-LABEL: name: hwpf1
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# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
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# CHECK: LDRWui %[[BASE]], 0
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@ -17,7 +12,7 @@ body: |
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bb.0:
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liveins: %w0, %x1
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%w2 = LDRWui %x1, 0 :: ("aarch64-strided-access" load 4 from @g)
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%w2 = LDRWui %x1, 0 :: ("aarch64-strided-access" load 4)
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%w2 = LDRWui %x1, 1
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%w0 = SUBWri %w0, 1, 0
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@ -28,19 +23,147 @@ body: |
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RET_ReallyLR
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...
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---
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# Verify that the tag collision between the loads is resolved and written back for post increment addressing.
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# CHECK-LABEL: name: hwpf2
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# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
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# CHECK: LDRWpost %[[BASE]], 0
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# CHECK: %x1 = ORRXrs %xzr, %[[BASE]], 0
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# CHECK: LDRWui %x1, 1
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# CHECK: LD1i64 %q2, 0, %[[BASE]]
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# CHECK: LDRWui %x1, 0
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name: hwpf2
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: %w0, %x1, %q2
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%q2 = LD1i64 %q2, 0, %x1 :: ("aarch64-strided-access" load 4)
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%w2 = LDRWui %x1, 0
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%w0 = SUBWri %w0, 1, 0
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%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
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Bcc 9, %bb.0, implicit %nzcv
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bb.1:
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RET_ReallyLR
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...
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---
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# CHECK-LABEL: name: hwpf3
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# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
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# CHECK: LD1i8 %q2, 0, %[[BASE]]
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# CHECK: LDRWui %x1, 0
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name: hwpf3
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: %w0, %x1, %q2
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%q2 = LD1i8 %q2, 0, %x1 :: ("aarch64-strided-access" load 4)
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%w0 = LDRWui %x1, 0
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%w0 = SUBWri %w0, 1, 0
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%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
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Bcc 9, %bb.0, implicit %nzcv
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bb.1:
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RET_ReallyLR
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...
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---
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# CHECK-LABEL: name: hwpf4
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# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
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# CHECK: LD1Onev1d %[[BASE]]
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# CHECK: LDRWui %x1, 0
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name: hwpf4
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: %w0, %x1
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%x1, %w2 = LDRWpost %x1, 0 :: ("aarch64-strided-access" load 4 from @g)
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%d2 = LD1Onev1d %x1 :: ("aarch64-strided-access" load 4)
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%w2 = LDRWui %x1, 0
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%w0 = SUBWri %w0, 1, 0
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%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
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Bcc 9, %bb.0, implicit %nzcv
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bb.1:
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RET_ReallyLR
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...
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---
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# CHECK-LABEL: name: hwpf5
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# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
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# CHECK: LD1Twov1d %[[BASE]]
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# CHECK: LDRWui %x1, 0
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name: hwpf5
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: %w0, %x1
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%d2_d3 = LD1Twov1d %x1 :: ("aarch64-strided-access" load 4)
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%w0 = LDRWui %x1, 0
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%w0 = SUBWri %w0, 1, 0
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%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
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Bcc 9, %bb.0, implicit %nzcv
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bb.1:
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RET_ReallyLR
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...
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---
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# CHECK-LABEL: name: hwpf6
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# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
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# CHECK: LDPQi %[[BASE]]
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# CHECK: LDRWui %x1, 3
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name: hwpf6
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: %w0, %x1
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%q2, %q3 = LDPQi %x1, 3 :: ("aarch64-strided-access" load 4)
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%w0 = LDRWui %x1, 3
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%w0 = SUBWri %w0, 1, 0
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%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
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Bcc 9, %bb.0, implicit %nzcv
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bb.1:
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RET_ReallyLR
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...
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---
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# CHECK-LABEL: name: hwpf7
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# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
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# CHECK: LDPXi %[[BASE]]
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# CHECK: LDRWui %x1, 2
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name: hwpf7
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: %w0, %x1
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%x2, %x3 = LDPXi %x1, 3 :: ("aarch64-strided-access" load 4)
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%w2 = LDRWui %x1, 2
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%w0 = SUBWri %w0, 1, 0
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%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
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Bcc 9, %bb.0, implicit %nzcv
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bb.1:
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RET_ReallyLR
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...
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---
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# Verify that the tag collision between the loads is resolved and written back
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# for post increment addressing for various load opcodes.
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# CHECK-LABEL: name: hwpfinc1
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# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
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# CHECK: LDRWpost %[[BASE]], 0
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# CHECK: %x1 = ORRXrs %xzr, %[[BASE]], 0
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# CHECK: LDRWui %x1, 1
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name: hwpfinc1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: %w0, %x1
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%x1, %w2 = LDRWpost %x1, 0 :: ("aarch64-strided-access" load 4)
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%w2 = LDRWui %x1, 1
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%w0 = SUBWri %w0, 1, 0
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@ -50,3 +173,135 @@ body: |
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bb.1:
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RET_ReallyLR
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...
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---
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# CHECK-LABEL: name: hwpfinc2
|
||||
# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
|
||||
# CHECK: LD1i64_POST %q2, 0, %[[BASE]]
|
||||
# CHECK: %x1 = ORRXrs %xzr, %[[BASE]], 0
|
||||
# CHECK: LDRWui %x1, 1
|
||||
name: hwpfinc2
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0, %x1, %q2
|
||||
|
||||
%x1, %q2 = LD1i64_POST %q2, 0, %x1, %x1 :: ("aarch64-strided-access" load 4)
|
||||
%w2 = LDRWui %x1, 132
|
||||
|
||||
%w0 = SUBWri %w0, 1, 0
|
||||
%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
|
||||
Bcc 9, %bb.0, implicit %nzcv
|
||||
|
||||
bb.1:
|
||||
RET_ReallyLR
|
||||
...
|
||||
---
|
||||
# CHECK-LABEL: name: hwpfinc3
|
||||
# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
|
||||
# CHECK: LD1i8_POST %q2, 0, %[[BASE]]
|
||||
# CHECK: %x1 = ORRXrs %xzr, %[[BASE]], 0
|
||||
# CHECK: LDRWui %x1, 132
|
||||
name: hwpfinc3
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0, %x1, %q2
|
||||
|
||||
%x1, %q2 = LD1i8_POST %q2, 0, %x1, %x1 :: ("aarch64-strided-access" load 4)
|
||||
%w0 = LDRWui %x1, 132
|
||||
|
||||
%w0 = SUBWri %w0, 1, 0
|
||||
%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
|
||||
Bcc 9, %bb.0, implicit %nzcv
|
||||
|
||||
bb.1:
|
||||
RET_ReallyLR
|
||||
...
|
||||
---
|
||||
# CHECK-LABEL: name: hwpfinc4
|
||||
# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
|
||||
# CHECK: LD1Rv1d_POST %[[BASE]]
|
||||
# CHECK: %x1 = ORRXrs %xzr, %[[BASE]], 0
|
||||
# CHECK: LDRWui %x1, 252
|
||||
name: hwpfinc4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0, %x1, %q2
|
||||
|
||||
%x1, %d2 = LD1Rv1d_POST %x1, %xzr :: ("aarch64-strided-access" load 4)
|
||||
%w2 = LDRWui %x1, 252
|
||||
|
||||
%w0 = SUBWri %w0, 1, 0
|
||||
%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
|
||||
Bcc 9, %bb.0, implicit %nzcv
|
||||
|
||||
bb.1:
|
||||
RET_ReallyLR
|
||||
...
|
||||
---
|
||||
# CHECK-LABEL: name: hwpfinc5
|
||||
# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
|
||||
# CHECK: LD3Threev2s_POST %[[BASE]]
|
||||
# CHECK: %x1 = ORRXrs %xzr, %[[BASE]], 0
|
||||
# CHECK: LDRWroX %x17, %x0
|
||||
name: hwpfinc5
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0, %x1, %x17, %q2
|
||||
|
||||
%x1, %d2_d3_d4 = LD3Threev2s_POST %x1, %x0 :: ("aarch64-strided-access" load 4)
|
||||
%w0 = LDRWroX %x17, %x0, 0, 0
|
||||
|
||||
%w0 = SUBWri %w0, 1, 0
|
||||
%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
|
||||
Bcc 9, %bb.0, implicit %nzcv
|
||||
|
||||
bb.1:
|
||||
RET_ReallyLR
|
||||
...
|
||||
---
|
||||
# CHECK-LABEL: name: hwpfinc6
|
||||
# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
|
||||
# CHECK: LDPDpost %[[BASE]]
|
||||
# CHECK: %x1 = ORRXrs %xzr, %[[BASE]], 0
|
||||
# CHECK: LDRWui %x17, 2
|
||||
name: hwpfinc6
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0, %x1, %x17, %q2
|
||||
|
||||
%x1, %d2, %d3 = LDPDpost %x1, 3 :: ("aarch64-strided-access" load 4)
|
||||
%w16 = LDRWui %x17, 2
|
||||
|
||||
%w0 = SUBWri %w0, 1, 0
|
||||
%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
|
||||
Bcc 9, %bb.0, implicit %nzcv
|
||||
|
||||
bb.1:
|
||||
RET_ReallyLR
|
||||
...
|
||||
---
|
||||
# CHECK-LABEL: name: hwpfinc7
|
||||
# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0
|
||||
# CHECK: LDPXpost %[[BASE]]
|
||||
# CHECK: %x1 = ORRXrs %xzr, %[[BASE]], 0
|
||||
# CHECK: LDRWui %x17, 2
|
||||
name: hwpfinc7
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0, %x1, %x17, %q2
|
||||
|
||||
%x1, %x2, %x3 = LDPXpost %x1, 3 :: ("aarch64-strided-access" load 4)
|
||||
%w18 = LDRWui %x17, 2
|
||||
|
||||
%w0 = SUBWri %w0, 1, 0
|
||||
%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
|
||||
Bcc 9, %bb.0, implicit %nzcv
|
||||
|
||||
bb.1:
|
||||
RET_ReallyLR
|
||||
...
|
||||
|
|
|
|||
Loading…
Reference in New Issue