forked from OSchip/llvm-project
parent
d18b16034a
commit
a4a49e37ab
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@ -1183,7 +1183,10 @@ X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
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RC = X86::FR64RegisterClass;
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else {
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assert(MVT::isVector(RegVT));
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RC = X86::VR128RegisterClass;
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if (MVT::getSizeInBits(RegVT) == 64)
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RC = X86::VR64RegisterClass;
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else
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RC = X86::VR128RegisterClass;
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}
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unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
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