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[RISCV][MC] Add minimal support for Ztso extension 

This is a minimalist implementation which simply adds the extension (in the experimental namespace since its not ratified), and wires up the setting of the required ELF header flag. Future changes will include codegen changes to exploit the stronger memory model.

This is intended to implement v0.1 of the proposed specification which can be found in Chapter 25 of https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf.

Differential Revision: https://reviews.llvm.org/D133239
This commit is contained in:
Philip Reames 2022-09-07 08:45:50 -07:00 committed by Philip Reames
parent 85b289377b
commit a4a29438f4
8 changed files with 31 additions and 0 deletions
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8
clang/test/Preprocessor/riscv-target-features.c
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@ -462,3 +462,11 @@
// RUN: %clang -target riscv64 -march=rv64izicbop -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICBOP-EXT %s
// CHECK-ZICBOP-EXT: __riscv_zicbop 1000000{{$}}
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv32iztso0p1 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv64iztso0p1 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s
// CHECK-ZTSO-EXT: __riscv_ztso 1000{{$}}

1
llvm/lib/Support/RISCVISAInfo.cpp
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@ -114,6 +114,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zbt", RISCVExtensionVersion{0, 93}},
{"zca", RISCVExtensionVersion{0, 70}},
{"zvfh", RISCVExtensionVersion{0, 1}},
{"ztso", RISCVExtensionVersion{0, 1}},
};
static bool stripExperimentalPrefix(StringRef &Ext) {

2
llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
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@ -157,6 +157,8 @@ void RISCVTargetELFStreamer::finish() {
if (Features[RISCV::FeatureStdExtC])
EFlags |= ELF::EF_RISCV_RVC;
if (Features[RISCV::FeatureStdExtZtso])
EFlags |= ELF::EF_RISCV_TSO;
switch (ABI) {
case RISCVABI::ABI_ILP32:

7
llvm/lib/Target/RISCV/RISCV.td
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@ -454,6 +454,13 @@ def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
AssemblerPredicate<(all_of FeatureStdExtZicbop),
"'Zicbop' (Cache-Block Prefetch Instructions)">;
def FeatureStdExtZtso
: SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true",
"'Ztso' (Memory Model - Total Store Order)">;
def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZTso()">,
AssemblerPredicate<(all_of FeatureStdExtZtso),
"'Ztso' (Memory Model - Total Store Order)">;
// Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
// tuning CPU names.
def Feature32Bit

2
llvm/lib/Target/RISCV/RISCVSubtarget.h
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@ -92,6 +92,7 @@ private:
bool HasStdExtZicboz = false;
bool HasStdExtZicbop = false;
bool HasStdExtZmmul = false;
bool HasStdExtZtso = false;
bool HasRV32 = false;
bool HasRV64 = false;
bool IsRV32E = false;
@ -192,6 +193,7 @@ public:
bool hasStdExtZicboz() const { return HasStdExtZicboz; }
bool hasStdExtZicbop() const { return HasStdExtZicbop; }
bool hasStdExtZmmul() const { return HasStdExtZmmul; }
bool hasStdExtZtso() const { return HasStdExtZtso; }
bool is64Bit() const { return HasRV64; }
bool isRV32E() const { return IsRV32E; }
bool enableLinkerRelax() const { return EnableLinkerRelax; }

2
llvm/test/CodeGen/RISCV/attributes.ll
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@ -84,6 +84,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV64ZICBOM %s
; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
; RV32M: .attribute 5, "rv32i2p0_m2p0"
; RV32ZMMUL: .attribute 5, "rv32i2p0_zmmul1p0"
@ -170,6 +171,7 @@
; RV64ZICBOM: .attribute 5, "rv64i2p0_zicbom1p0"
; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0"
; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1

3
llvm/test/MC/RISCV/attribute-arch.s
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@ -196,3 +196,6 @@
.attribute arch, "rv32izca0p70"
# CHECK: attribute 5, "rv32i2p0_zca0p70"
.attribute arch, "rv32iztso0p1"
# CHECK: attribute 5, "rv32i2p0_ztso0p1"

6
llvm/test/MC/RISCV/elf-flags.s
View File

@ -5,6 +5,8 @@
# RUN: llvm-mc -triple=riscv32 -mattr=+e -filetype=obj < %s \
# RUN: | llvm-readobj --file-headers - \
# RUN: | FileCheck -check-prefix=CHECK-RVE %s
# RUN: llvm-mc -triple=riscv32 -mattr=+experimental-ztso -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-TSO %s
# RUN: llvm-mc -triple=riscv64 -mattr=+experimental-ztso -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-TSO %s
# CHECK-RVI: Flags [ (0x0)
# CHECK-RVI-NEXT: ]
@ -17,4 +19,8 @@
# CHECK-RVE-NEXT: EF_RISCV_RVE (0x8)
# CHECK-RVE-NEXT: ]
# CHECK-TSO: Flags [ (0x10)
# CHECK-NEXT-TSO EF_RISCV_TSO (0x10)
# CHECK-NEXT-TSO ]
nop