From a4a29438f451370ed241dde30bfcaab0fdf2ab71 Mon Sep 17 00:00:00 2001 From: Philip Reames Date: Wed, 7 Sep 2022 08:45:50 -0700 Subject: [PATCH] [RISCV][MC] Add minimal support for Ztso extension This is a minimalist implementation which simply adds the extension (in the experimental namespace since its not ratified), and wires up the setting of the required ELF header flag. Future changes will include codegen changes to exploit the stronger memory model. This is intended to implement v0.1 of the proposed specification which can be found in Chapter 25 of https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf. Differential Revision: https://reviews.llvm.org/D133239 --- clang/test/Preprocessor/riscv-target-features.c | 8 ++++++++ llvm/lib/Support/RISCVISAInfo.cpp | 1 + llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp | 2 ++ llvm/lib/Target/RISCV/RISCV.td | 7 +++++++ llvm/lib/Target/RISCV/RISCVSubtarget.h | 2 ++ llvm/test/CodeGen/RISCV/attributes.ll | 2 ++ llvm/test/MC/RISCV/attribute-arch.s | 3 +++ llvm/test/MC/RISCV/elf-flags.s | 6 ++++++ 8 files changed, 31 insertions(+) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index deb333c46ded..9ec91171e8f0 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -462,3 +462,11 @@ // RUN: %clang -target riscv64 -march=rv64izicbop -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZICBOP-EXT %s // CHECK-ZICBOP-EXT: __riscv_zicbop 1000000{{$}} + +// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ +// RUN: -march=rv32iztso0p1 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s +// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ +// RUN: -march=rv64iztso0p1 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s +// CHECK-ZTSO-EXT: __riscv_ztso 1000{{$}} diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index a666337ee561..8deedfb8c8fd 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -114,6 +114,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { {"zbt", RISCVExtensionVersion{0, 93}}, {"zca", RISCVExtensionVersion{0, 70}}, {"zvfh", RISCVExtensionVersion{0, 1}}, + {"ztso", RISCVExtensionVersion{0, 1}}, }; static bool stripExperimentalPrefix(StringRef &Ext) { diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp index c5f8a42bab6a..fef8cb2798a3 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp @@ -157,6 +157,8 @@ void RISCVTargetELFStreamer::finish() { if (Features[RISCV::FeatureStdExtC]) EFlags |= ELF::EF_RISCV_RVC; + if (Features[RISCV::FeatureStdExtZtso]) + EFlags |= ELF::EF_RISCV_TSO; switch (ABI) { case RISCVABI::ABI_ILP32: diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index 6d9836f28a1b..b4f341685774 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -454,6 +454,13 @@ def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">, AssemblerPredicate<(all_of FeatureStdExtZicbop), "'Zicbop' (Cache-Block Prefetch Instructions)">; +def FeatureStdExtZtso + : SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true", + "'Ztso' (Memory Model - Total Store Order)">; +def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZTso()">, + AssemblerPredicate<(all_of FeatureStdExtZtso), + "'Ztso' (Memory Model - Total Store Order)">; + // Feature32Bit exists to mark CPUs that support RV32 to distinquish them from // tuning CPU names. def Feature32Bit diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h index 461968d40311..3c95e062a13d 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -92,6 +92,7 @@ private: bool HasStdExtZicboz = false; bool HasStdExtZicbop = false; bool HasStdExtZmmul = false; + bool HasStdExtZtso = false; bool HasRV32 = false; bool HasRV64 = false; bool IsRV32E = false; @@ -192,6 +193,7 @@ public: bool hasStdExtZicboz() const { return HasStdExtZicboz; } bool hasStdExtZicbop() const { return HasStdExtZicbop; } bool hasStdExtZmmul() const { return HasStdExtZmmul; } + bool hasStdExtZtso() const { return HasStdExtZtso; } bool is64Bit() const { return HasRV64; } bool isRV32E() const { return IsRV32E; } bool enableLinkerRelax() const { return EnableLinkerRelax; } diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 5c693d2c36f2..88921ee7baa2 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -84,6 +84,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV64ZICBOM %s ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s ; RV32M: .attribute 5, "rv32i2p0_m2p0" ; RV32ZMMUL: .attribute 5, "rv32i2p0_zmmul1p0" @@ -170,6 +171,7 @@ ; RV64ZICBOM: .attribute 5, "rv64i2p0_zicbom1p0" ; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0" ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0" +; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1" define i32 @addi(i32 %a) { %1 = add i32 %a, 1 diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 9b9eb1c09315..3ad7f1d1df37 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -196,3 +196,6 @@ .attribute arch, "rv32izca0p70" # CHECK: attribute 5, "rv32i2p0_zca0p70" + +.attribute arch, "rv32iztso0p1" +# CHECK: attribute 5, "rv32i2p0_ztso0p1" diff --git a/llvm/test/MC/RISCV/elf-flags.s b/llvm/test/MC/RISCV/elf-flags.s index 7e17377b34d5..543eadede1f7 100644 --- a/llvm/test/MC/RISCV/elf-flags.s +++ b/llvm/test/MC/RISCV/elf-flags.s @@ -5,6 +5,8 @@ # RUN: llvm-mc -triple=riscv32 -mattr=+e -filetype=obj < %s \ # RUN: | llvm-readobj --file-headers - \ # RUN: | FileCheck -check-prefix=CHECK-RVE %s +# RUN: llvm-mc -triple=riscv32 -mattr=+experimental-ztso -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-TSO %s +# RUN: llvm-mc -triple=riscv64 -mattr=+experimental-ztso -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-TSO %s # CHECK-RVI: Flags [ (0x0) # CHECK-RVI-NEXT: ] @@ -17,4 +19,8 @@ # CHECK-RVE-NEXT: EF_RISCV_RVE (0x8) # CHECK-RVE-NEXT: ] +# CHECK-TSO: Flags [ (0x10) +# CHECK-NEXT-TSO EF_RISCV_TSO (0x10) +# CHECK-NEXT-TSO ] + nop