[Sparc] Fix incorrect MI insertion position for spilling f128.

Summary:
Obviously, new built MI (sethi+add or sethi+xor+add) for constructing large offset
should be inserted before new created MI for storing even register into memory.
So the insertion position should be *StMI instead of II.

before fixed:

std %f0, [%g1+80]
sethi 4, %g1        <<<
add %g1, %sp, %g1   <<< this two instructions should be put before "std %f0, [%g1+80]".
sethi 4, %g1
add %g1, %sp, %g1
std %f2, [%g1+88]

after fixed:

sethi 4, %g1
add %g1, %sp, %g1
std %f0, [%g1+80]
sethi 4, %g1
add %g1, %sp, %g1
std %f2, [%g1+88]

Reviewers: venkatra, jyknight

Reviewed By: jyknight

Subscribers: jyknight, fedor.sergeev, jrtc27, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60397

llvm-svn: 358042
This commit is contained in:
Jim Lin 2019-04-10 01:56:32 +00:00
parent 9ca3a95f79
commit a49c95e02a
2 changed files with 25 additions and 2 deletions

View File

@ -188,7 +188,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MachineInstr *StMI =
BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))
.addReg(FrameReg).addImm(0).addReg(SrcEvenReg);
replaceFI(MF, II, *StMI, dl, 0, Offset, FrameReg);
replaceFI(MF, *StMI, *StMI, dl, 0, Offset, FrameReg);
MI.setDesc(TII.get(SP::STDFri));
MI.getOperand(2).setReg(SrcOddReg);
Offset += 8;
@ -200,7 +200,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MachineInstr *StMI =
BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg)
.addReg(FrameReg).addImm(0);
replaceFI(MF, II, *StMI, dl, 1, Offset, FrameReg);
replaceFI(MF, *StMI, *StMI, dl, 1, Offset, FrameReg);
MI.setDesc(TII.get(SP::LDDFri));
MI.getOperand(0).setReg(DestOddReg);

View File

@ -53,6 +53,29 @@ entry:
ret void
}
; CHECK-LABEL: f128_spill_large:
; CHECK: sethi 4, %g1
; CHECK: sethi 4, %g1
; CHECK-NEXT: add %g1, %sp, %g1
; CHECK-NEXT: std %f{{.+}}, [%g1]
; CHECK: sethi 4, %g1
; CHECK-NEXT: add %g1, %sp, %g1
; CHECK-NEXT: std %f{{.+}}, [%g1+8]
; CHECK: sethi 4, %g1
; CHECK-NEXT: add %g1, %sp, %g1
; CHECK-NEXT: ldd [%g1], %f{{.+}}
; CHECK: sethi 4, %g1
; CHECK-NEXT: add %g1, %sp, %g1
; CHECK-NEXT: ldd [%g1+8], %f{{.+}}
define void @f128_spill_large(<251 x fp128>* noalias sret %scalar.result, <251 x fp128>* byval %a) {
entry:
%0 = load <251 x fp128>, <251 x fp128>* %a, align 8
call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"()
store <251 x fp128> %0, <251 x fp128>* %scalar.result, align 8
ret void
}
; CHECK-LABEL: f128_compare:
; HARD: fcmpq
; HARD-NEXT: nop