forked from OSchip/llvm-project
[ARM] Add basic masked load/store costs
This adds some basic MVE masked load/store costs, notably changing the cost of legal loads/stores to the MVECostFactor and the cost of scalarized instructions to 8*NumElts. Differential Revision: https://reviews.llvm.org/D86538
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@ -1318,6 +1318,24 @@ int ARMTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
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CostKind, I);
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CostKind, I);
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}
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}
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unsigned ARMTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
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Align Alignment,
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unsigned AddressSpace,
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TTI::TargetCostKind CostKind) {
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if (ST->hasMVEIntegerOps()) {
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if (Opcode == Instruction::Load && isLegalMaskedLoad(Src, Alignment))
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return ST->getMVEVectorCostFactor();
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if (Opcode == Instruction::Store && isLegalMaskedStore(Src, Alignment))
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return ST->getMVEVectorCostFactor();
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}
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if (!isa<FixedVectorType>(Src))
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return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
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CostKind);
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// Scalar cost, which is currently very high due to the efficiency of the
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// generated code.
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return cast<FixedVectorType>(Src)->getNumElements() * 8;
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}
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int ARMTTIImpl::getInterleavedMemoryOpCost(
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int ARMTTIImpl::getInterleavedMemoryOpCost(
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unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
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unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
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Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
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Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
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@ -229,6 +229,10 @@ public:
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TTI::TargetCostKind CostKind,
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TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr);
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const Instruction *I = nullptr);
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unsigned getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
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unsigned AddressSpace,
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TTI::TargetCostKind CostKind);
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int getInterleavedMemoryOpCost(
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int getInterleavedMemoryOpCost(
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unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
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unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
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Align Alignment, unsigned AddressSpace,
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Align Alignment, unsigned AddressSpace,
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