forked from OSchip/llvm-project
[SystemZ] Prefer LHI;ST... over LAY;MV...
If we had a store of an integer to memory, and the integer and store size
were suitable for a form of MV..., we used MV... no matter what. We could
then have sequences like:
lay %r2, 0(%r3,%r4)
mvi 0(%r2), 4
In these cases it seems better to force the constant into a register
and use a normal store:
lhi %r2, 4
stc %r2, 0(%r3, %r4)
since %r2 is more likely to be hoisted and is easier to rematerialize.
llvm-svn: 189098
This commit is contained in:
Richard Sandiford
parent
37cd6cfba2
commit
a481f58542
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@ -159,6 +159,12 @@ class SystemZDAGToDAGISel : public SelectionDAGISel {
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bool selectBDAddr(SystemZAddressingMode::DispRange DR, SDValue Addr,
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SDValue &Base, SDValue &Disp);
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// Try to match Addr as a FormBDX address with displacement type DR.
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// Return true on success and if the result had no index. Store the
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// base and displacement in Base and Disp respectively.
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bool selectMVIAddr(SystemZAddressingMode::DispRange DR, SDValue Addr,
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SDValue &Base, SDValue &Disp);
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// Try to match Addr as a FormBDX* address of form Form with
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// displacement type DR. Return true on success, storing the base,
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// displacement and index in Base, Disp and Index respectively.
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@ -189,6 +195,14 @@ class SystemZDAGToDAGISel : public SelectionDAGISel {
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return selectBDAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp);
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}
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// MVI matching routines used by SystemZOperands.td.
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bool selectMVIAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp) {
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return selectMVIAddr(SystemZAddressingMode::Disp12Pair, Addr, Base, Disp);
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}
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bool selectMVIAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp) {
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return selectMVIAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp);
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}
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// BDX matching routines used by SystemZOperands.td.
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bool selectBDXAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp,
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SDValue &Index) {
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@ -575,6 +589,17 @@ bool SystemZDAGToDAGISel::selectBDAddr(SystemZAddressingMode::DispRange DR,
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return true;
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}
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bool SystemZDAGToDAGISel::selectMVIAddr(SystemZAddressingMode::DispRange DR,
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SDValue Addr, SDValue &Base,
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SDValue &Disp) {
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SystemZAddressingMode AM(SystemZAddressingMode::FormBDXNormal, DR);
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if (!selectAddress(Addr, AM) || AM.Index.getNode())
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return false;
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getAddressOperands(AM, Addr.getValueType(), Base, Disp);
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return true;
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}
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bool SystemZDAGToDAGISel::selectBDXAddr(SystemZAddressingMode::AddrForm Form,
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SystemZAddressingMode::DispRange DR,
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SDValue Addr, SDValue &Base,
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@ -627,27 +627,33 @@ class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
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let mayStore = 1;
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}
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// StoreSI* instructions are used to store an integer to memory, but the
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// addresses are more restricted than for normal stores. If we are in the
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// situation of having to force either the address into a register or the
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// constant into a register, it's usually better to do the latter.
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// We therefore match the address in the same way as a normal store and
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// only use the StoreSI* instruction if the matched address is suitable.
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class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
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Immediate imm, AddressingMode mode = bdaddr12only>
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: InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
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Immediate imm>
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: InstSI<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
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mnemonic#"\t$BD1, $I2",
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[(operator imm:$I2, mode:$BD1)]> {
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[(operator imm:$I2, mviaddr12pair:$BD1)]> {
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let mayStore = 1;
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}
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class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
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Immediate imm, AddressingMode mode = bdaddr20only>
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: InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
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Immediate imm>
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: InstSIY<opcode, (outs), (ins mviaddr20pair:$BD1, imm:$I2),
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mnemonic#"\t$BD1, $I2",
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[(operator imm:$I2, mode:$BD1)]> {
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[(operator imm:$I2, mviaddr20pair:$BD1)]> {
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let mayStore = 1;
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}
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class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
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Immediate imm>
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: InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
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: InstSIL<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
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mnemonic#"\t$BD1, $I2",
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[(operator imm:$I2, bdaddr12only:$BD1)]> {
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[(operator imm:$I2, mviaddr12pair:$BD1)]> {
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let mayStore = 1;
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}
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@ -655,9 +661,9 @@ multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
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SDPatternOperator operator, Immediate imm> {
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let DispKey = mnemonic in {
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let DispSize = "12" in
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def "" : StoreSI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
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def "" : StoreSI<mnemonic, siOpcode, operator, imm>;
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let DispSize = "20" in
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def Y : StoreSIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
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def Y : StoreSIY<mnemonic#"y", siyOpcode, operator, imm>;
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}
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}
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@ -435,6 +435,7 @@ def BDLAddr64Disp12Len8 : AddressAsmOperand<"BDLAddr", "64", "12", "Len8">;
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// <type> is one of:
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// shift : base + displacement (32-bit)
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// bdaddr : base + displacement
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// mviaddr : like bdaddr, but reject cases with a natural index
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// bdxaddr : base + displacement + index
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// laaddr : like bdxaddr, but used for Load Address operations
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// dynalloc : base + displacement + index + ADJDYNALLOC
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@ -460,6 +461,8 @@ def bdaddr12only : BDMode <"BDAddr", "64", "12", "Only">;
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def bdaddr12pair : BDMode <"BDAddr", "64", "12", "Pair">;
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def bdaddr20only : BDMode <"BDAddr", "64", "20", "Only">;
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def bdaddr20pair : BDMode <"BDAddr", "64", "20", "Pair">;
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def mviaddr12pair : BDMode <"MVIAddr", "64", "12", "Pair">;
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def mviaddr20pair : BDMode <"MVIAddr", "64", "20", "Pair">;
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def bdxaddr12only : BDXMode<"BDXAddr", "64", "12", "Only">;
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def bdxaddr12pair : BDXMode<"BDXAddr", "64", "12", "Pair">;
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def bdxaddr20only : BDXMode<"BDXAddr", "64", "20", "Only">;
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@ -21,18 +21,21 @@ define i64 @f1(i64 %length, i64 %index) {
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;
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; CHECK-C-LABEL: f1:
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; CHECK-C: lgr %r15, [[ADDR:%r[1-5]]]
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; CHECK-C: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]])
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; CHECK-C: mvi 0([[TMP]]), 2
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; CHECK-C-DAG: la %r2, 160([[ADDR]])
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; CHECK-C-DAG: lhi [[TMP:%r[0-5]]], 2
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; CHECK-C: stc [[TMP]], 0({{%r3,%r2|%r2,%r3}})
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;
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; CHECK-D-LABEL: f1:
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; CHECK-D: lgr %r15, [[ADDR:%r[1-5]]]
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; CHECK-D: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]])
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; CHECK-D: mvi 4095([[TMP]]), 3
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; CHECK-D-DAG: la %r2, 160([[ADDR]])
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; CHECK-D-DAG: lhi [[TMP:%r[0-5]]], 3
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; CHECK-D: stc [[TMP]], 4095({{%r3,%r2|%r2,%r3}})
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;
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; CHECK-E-LABEL: f1:
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; CHECK-E: lgr %r15, [[ADDR:%r[1-5]]]
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; CHECK-E: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]])
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; CHECK-E: mviy 4096([[TMP]]), 4
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; CHECK-E-DAG: la %r2, 160([[ADDR]])
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; CHECK-E-DAG: lhi [[TMP:%r[0-5]]], 4
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; CHECK-E: stcy [[TMP]], 4096({{%r3,%r2|%r2,%r3}})
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%a = alloca i8, i64 %length
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store volatile i8 0, i8 *%a
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%b = getelementptr i8 *%a, i64 4095
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@ -182,17 +182,16 @@ define void @f8() {
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}
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; Check a case where the original displacement is out of range. The backend
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; should force an LAY from the outset. We don't yet do any kind of anchor
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; optimization, so there should be no offset on the MVHI itself.
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; should force STY to be used instead.
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define void @f9() {
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; CHECK-NOFP-LABEL: f9:
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; CHECK-NOFP: lay %r1, 12296(%r15)
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; CHECK-NOFP: mvhi 0(%r1), 42
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; CHECK-NOFP: lhi [[TMP:%r[0-5]]], 42
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; CHECK-NOFP: sty [[TMP]], 12296(%r15)
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; CHECK-NOFP: br %r14
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;
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; CHECK-FP-LABEL: f9:
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; CHECK-FP: lay %r1, 12296(%r11)
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; CHECK-FP: mvhi 0(%r1), 42
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; CHECK-FP: lhi [[TMP:%r[0-5]]], 42
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; CHECK-FP: sty [[TMP]], 12296(%r11)
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; CHECK-FP: br %r14
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%region1 = alloca [2006 x i32], align 8
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%region2 = alloca [2006 x i32], align 8
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@ -139,11 +139,11 @@ define void @f14(i8 *%src) {
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ret void
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}
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; Check that MVI does not allow an index
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; Check that MVI does not allow an index. We prefer STC in that case.
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define void @f15(i64 %src, i64 %index) {
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; CHECK-LABEL: f15:
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; CHECK: agr %r2, %r3
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; CHECK: mvi 4095(%r2), 42
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; CHECK: lhi [[TMP:%r[0-5]]], 42
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; CHECK: stc [[TMP]], 4095({{%r2,%r3|%r3,%r2}}
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 4095
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@ -152,11 +152,11 @@ define void @f15(i64 %src, i64 %index) {
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ret void
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}
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; Check that MVIY does not allow an index
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; Check that MVIY does not allow an index. We prefer STCY in that case.
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define void @f16(i64 %src, i64 %index) {
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; CHECK-LABEL: f16:
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; CHECK: agr %r2, %r3
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; CHECK: mviy 4096(%r2), 42
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; CHECK: lhi [[TMP:%r[0-5]]], 42
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; CHECK: stcy [[TMP]], 4096({{%r2,%r3|%r3,%r2}}
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 4096
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@ -75,34 +75,34 @@ define void @f8(i16 *%a) {
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ret void
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}
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; Check the next halfword up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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; Check the next halfword up, which is out of range. We prefer STHY
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; in that case.
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define void @f9(i16 *%a) {
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; CHECK-LABEL: f9:
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; CHECK: aghi %r2, 4096
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; CHECK: mvhhi 0(%r2), 42
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; CHECK: lhi [[TMP:%r[0-5]]], 42
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; CHECK: sthy [[TMP]], 4096(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i16 *%a, i64 2048
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store i16 42, i16 *%ptr
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ret void
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}
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; Check negative displacements, which also need separate address logic.
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; Check negative displacements, for which we again prefer STHY.
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define void @f10(i16 *%a) {
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; CHECK-LABEL: f10:
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; CHECK: aghi %r2, -2
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; CHECK: mvhhi 0(%r2), 42
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; CHECK: lhi [[TMP:%r[0-5]]], 42
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; CHECK: sthy [[TMP]], -2(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i16 *%a, i64 -1
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store i16 42, i16 *%ptr
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ret void
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}
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; Check that MVHHI does not allow an index
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; Check that MVHHI does not allow an index.
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define void @f11(i64 %src, i64 %index) {
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; CHECK-LABEL: f11:
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; CHECK: agr %r2, %r3
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; CHECK: mvhhi 0(%r2), 42
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; CHECK: lhi [[TMP:%r[0-5]]], 42
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; CHECK: sth [[TMP]], 0({{%r2,%r3|%r3,%r2}})
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; CHECK: br %r14
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%add = add i64 %src, %index
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%ptr = inttoptr i64 %add to i16 *
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@ -66,34 +66,33 @@ define void @f7(i32 *%a) {
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ret void
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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; Check the next word up, which is out of range. We prefer STY in that case.
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define void @f8(i32 *%a) {
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; CHECK-LABEL: f8:
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; CHECK: aghi %r2, 4096
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; CHECK: mvhi 0(%r2), 42
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; CHECK: lhi [[TMP:%r[0-5]]], 42
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; CHECK: sty [[TMP]], 4096(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%a, i64 1024
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store i32 42, i32 *%ptr
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ret void
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}
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; Check negative displacements, which also need separate address logic.
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; Check negative displacements, for which we again prefer STY.
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define void @f9(i32 *%a) {
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; CHECK-LABEL: f9:
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; CHECK: aghi %r2, -4
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; CHECK: mvhi 0(%r2), 42
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; CHECK: lhi [[TMP:%r[0-5]]], 42
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; CHECK: sty [[TMP]], -4(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%a, i64 -1
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store i32 42, i32 *%ptr
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ret void
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}
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; Check that MVHI does not allow an index
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; Check that MVHI does not allow an index.
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define void @f10(i64 %src, i64 %index) {
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; CHECK-LABEL: f10:
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; CHECK: agr %r2, %r3
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; CHECK: mvhi 0(%r2), 42
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; CHECK: lhi [[TMP:%r[0-5]]], 42
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; CHECK: st [[TMP]], 0({{%r2,%r3|%r3,%r2}})
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; CHECK: br %r14
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%add = add i64 %src, %index
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%ptr = inttoptr i64 %add to i32 *
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@ -66,34 +66,34 @@ define void @f7(i64 *%a) {
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ret void
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}
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; Check the next doubleword up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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; Check the next doubleword up, which is out of range. We prefer STG
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; in that case.
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define void @f8(i64 *%a) {
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; CHECK-LABEL: f8:
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; CHECK: aghi %r2, 4096
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; CHECK: mvghi 0(%r2), 42
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; CHECK: lghi [[TMP:%r[0-5]]], 42
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; CHECK: stg [[TMP]], 4096(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%a, i64 512
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store i64 42, i64 *%ptr
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ret void
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}
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; Check negative displacements, which also need separate address logic.
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; Check negative displacements, for which we again prefer STG.
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define void @f9(i64 *%a) {
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; CHECK-LABEL: f9:
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; CHECK: aghi %r2, -8
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; CHECK: mvghi 0(%r2), 42
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; CHECK: lghi [[TMP:%r[0-5]]], 42
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; CHECK: stg [[TMP]], -8(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%a, i64 -1
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store i64 42, i64 *%ptr
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ret void
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}
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; Check that MVGHI does not allow an index
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; Check that MVGHI does not allow an index.
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define void @f10(i64 %src, i64 %index) {
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; CHECK-LABEL: f10:
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; CHECK: agr %r2, %r3
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; CHECK: mvghi 0(%r2), 42
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; CHECK: lghi [[TMP:%r[0-5]]], 42
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; CHECK: stg [[TMP]], 0({{%r2,%r3|%r3,%r2}})
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; CHECK: br %r14
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%add = add i64 %src, %index
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%ptr = inttoptr i64 %add to i64 *
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