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AVX-512: added calling conventions for i1 vectors. 

Fixed bug: https://llvm.org/bugs/show_bug.cgi?id=20724

llvm-svn: 235889
This commit is contained in:
Elena Demikhovsky 2015-04-27 15:11:19 +00:00
parent 398732979a
commit a480ef5494
3 changed files with 71 additions and 3 deletions
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20
llvm/lib/Target/X86/X86CallingConv.td
View File

@ -39,6 +39,16 @@ def RetCC_X86Common : CallingConv<[
CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
// Boolean vectors of AVX-512 are returned in SIMD registers.
// The call from AVX to AVX-512 function should work,
// since the boolean types in AVX/AVX2 are promoted by default.
CCIfType<[v2i1], CCPromoteToType<v2i64>>,
CCIfType<[v4i1], CCPromoteToType<v4i32>>,
CCIfType<[v8i1], CCPromoteToType<v8i16>>,
CCIfType<[v16i1], CCPromoteToType<v16i8>>,
CCIfType<[v32i1], CCPromoteToType<v32i8>>,
CCIfType<[v64i1], CCPromoteToType<v64i8>>,
// Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3
// can only be used by ABI non-compliant code. If the target doesn't have XMM
// registers, it won't have vector types.
@ -258,6 +268,16 @@ def CC_X86_64_C : CallingConv<[
CCIfSubtarget<"hasSSE2()",
CCPromoteToType<v2i64>>>>,
// Boolean vectors of AVX-512 are returned in SIMD registers.
// The call from AVX to AVX-512 function should work,
// since the boolean types in AVX/AVX2 are promoted by default.
CCIfType<[v2i1], CCPromoteToType<v2i64>>,
CCIfType<[v4i1], CCPromoteToType<v4i32>>,
CCIfType<[v8i1], CCPromoteToType<v8i16>>,
CCIfType<[v16i1], CCPromoteToType<v16i8>>,
CCIfType<[v32i1], CCPromoteToType<v32i8>>,
CCIfType<[v64i1], CCPromoteToType<v64i8>>,
// The first 8 FP/Vector arguments are passed in XMM registers.
CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
CCIfSubtarget<"hasSSE1()",

10
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -1907,8 +1907,12 @@ X86TargetLowering::LowerReturn(SDValue Chain,
ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
else if (VA.getLocInfo() == CCValAssign::ZExt)
ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
else if (VA.getLocInfo() == CCValAssign::AExt)
ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
else if (VA.getLocInfo() == CCValAssign::AExt) {
if (ValVT.getScalarType() == MVT::i1)
ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
else
ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
}
else if (VA.getLocInfo() == CCValAssign::BCvt)
ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
@ -2376,7 +2380,7 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
if (VA.isExtInLoc()) {
// Handle MMX values passed in XMM regs.
if (RegVT.isVector())
if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
else
ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);

44
llvm/test/CodeGen/X86/avx512-calling-conv.ll Normal file
View File

@ -0,0 +1,44 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s --check-prefix=KNL
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck %s --check-prefix=SKX
; KNL-LABEL: test1
; KNL: vxorps
define <16 x i1> @test1() {
ret <16 x i1> zeroinitializer
}
; SKX-LABEL: test2
; SKX: vpmovb2m
; SKX: vpmovb2m
; SKX: kandw
; SKX: vpmovm2b
; KNL-LABEL: test2
; KNL: vpmovsxbd
; KNL: vpmovsxbd
; KNL: vpandd
; KNL: vpmovdb
define <16 x i1> @test2(<16 x i1>%a, <16 x i1>%b) {
%c = and <16 x i1>%a, %b
ret <16 x i1> %c
}
; SKX-LABEL: test3
; SKX: vpmovw2m
; SKX: vpmovw2m
; SKX: kandb
; SKX: vpmovm2w
define <8 x i1> @test3(<8 x i1>%a, <8 x i1>%b) {
%c = and <8 x i1>%a, %b
ret <8 x i1> %c
}
; SKX-LABEL: test4
; SKX: vpmovd2m
; SKX: vpmovd2m
; SKX: kandw
; SKX: vpmovm2d
define <4 x i1> @test4(<4 x i1>%a, <4 x i1>%b) {
%c = and <4 x i1>%a, %b
ret <4 x i1> %c
}