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[SelectionDAG] GetDemandedBits - update SIGN_EXTEND_INREG op to just call SimplifyMultipleUseDemandedBits. 

llvm-svn: 367098
This commit is contained in:
Simon Pilgrim 2019-07-26 10:03:07 +00:00
parent 00e89b428b
commit a424a1f351
1 changed files with 1 additions and 9 deletions
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10
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -2154,6 +2154,7 @@ SDValue SelectionDAG::GetDemandedBits(SDValue V, const APInt &DemandedBits,
}
case ISD::OR:
case ISD::XOR:
case ISD::SIGN_EXTEND_INREG:
return TLI->SimplifyMultipleUseDemandedBits(V, DemandedBits, DemandedElts,
*this, 0);
case ISD::SRL:
@ -2199,15 +2200,6 @@ SDValue SelectionDAG::GetDemandedBits(SDValue V, const APInt &DemandedBits,
return getNode(ISD::ANY_EXTEND, SDLoc(V), V.getValueType(), DemandedSrc);
break;
}
case ISD::SIGN_EXTEND_INREG:
EVT ExVT = cast<VTSDNode>(V.getOperand(1))->getVT();
unsigned ExVTBits = ExVT.getScalarSizeInBits();
// If none of the extended bits are demanded, eliminate the sextinreg.
if (DemandedBits.getActiveBits() <= ExVTBits)
return V.getOperand(0);
break;
}
return SDValue();
}