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[DAGCombiner] reduce code duplication with local variables; NFCI 

llvm-svn: 298954
This commit is contained in:
Sanjay Patel 2017-03-28 22:45:53 +00:00
parent f07a9995e8
commit a41a5c29f0
1 changed files with 21 additions and 21 deletions
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42
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -3181,13 +3181,17 @@ SDValue DAGCombiner::foldAndOfSetCCs(SDValue N0, SDValue N1, const SDLoc &DL) {
ISD::CondCode CC0 = cast<CondCodeSDNode>(N0CC)->get();
ISD::CondCode CC1 = cast<CondCodeSDNode>(N1CC)->get();
EVT VT = N1.getValueType();
assert(VT == N0.getValueType() && "Unexpected operand types for 'and'");
EVT LLVT = LL.getValueType();
EVT LRVT = LR.getValueType();
bool IsInteger = LLVT.isInteger();
if (LR == RR && CC0 == CC1 && LL.getValueType().isInteger()) {
EVT CCVT = getSetCCResultType(LR.getValueType());
if (LR == RR && CC0 == CC1 && IsInteger) {
EVT CCVT = getSetCCResultType(LRVT);
// fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
if (isNullConstant(LR) && CC1 == ISD::SETEQ) {
if (VT == CCVT || (!LegalOperations && VT == MVT::i1)) {
SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), LR.getValueType(), LL, RL);
SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), LRVT, LL, RL);
AddToWorklist(Or.getNode());
return DAG.getSetCC(DL, VT, Or, LR, CC1);
}
@ -3196,8 +3200,7 @@ SDValue DAGCombiner::foldAndOfSetCCs(SDValue N0, SDValue N1, const SDLoc &DL) {
// fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
if (CC1 == ISD::SETEQ) {
if (VT == CCVT || (!LegalOperations && VT == MVT::i1)) {
SDValue And =
DAG.getNode(ISD::AND, SDLoc(N0), LR.getValueType(), LL, RL);
SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), LRVT, LL, RL);
AddToWorklist(And.getNode());
return DAG.getSetCC(DL, VT, And, LR, CC1);
}
@ -3205,8 +3208,7 @@ SDValue DAGCombiner::foldAndOfSetCCs(SDValue N0, SDValue N1, const SDLoc &DL) {
// fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
if (CC1 == ISD::SETGT) {
if (VT == CCVT || (!LegalOperations && VT == MVT::i1)) {
SDValue Or =
DAG.getNode(ISD::OR, SDLoc(N0), LR.getValueType(), LL, RL);
SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), LRVT, LL, RL);
AddToWorklist(Or.getNode());
return DAG.getSetCC(DL, VT, Or, LR, CC1);
}
@ -3215,17 +3217,17 @@ SDValue DAGCombiner::foldAndOfSetCCs(SDValue N0, SDValue N1, const SDLoc &DL) {
}
// Simplify (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)
if (LL == RL && CC0 == CC1 && LL.getValueType().isInteger() &&
CC0 == ISD::SETNE && ((isNullConstant(LR) && isAllOnesConstant(RR)) ||
(isAllOnesConstant(LR) && isNullConstant(RR)))) {
EVT CCVT = getSetCCResultType(LL.getValueType());
if (LL == RL && CC0 == CC1 && IsInteger && CC0 == ISD::SETNE &&
((isNullConstant(LR) && isAllOnesConstant(RR)) ||
(isAllOnesConstant(LR) && isNullConstant(RR)))) {
EVT CCVT = getSetCCResultType(LLVT);
if (VT == CCVT || (!LegalOperations && VT == MVT::i1)) {
SDLoc DL0(N0);
SDValue Add = DAG.getNode(ISD::ADD, DL0, LL.getValueType(), LL,
DAG.getConstant(1, DL, LL.getValueType()));
SDValue Add =
DAG.getNode(ISD::ADD, DL0, LLVT, LL, DAG.getConstant(1, DL, LLVT));
AddToWorklist(Add.getNode());
return DAG.getSetCC(
DL, VT, Add, DAG.getConstant(2, DL, LL.getValueType()), ISD::SETUGE);
return DAG.getSetCC(DL, VT, Add, DAG.getConstant(2, DL, LLVT),
ISD::SETUGE);
}
}
@ -3235,16 +3237,14 @@ SDValue DAGCombiner::foldAndOfSetCCs(SDValue N0, SDValue N1, const SDLoc &DL) {
std::swap(RL, RR);
}
if (LL == RL && LR == RR) {
bool IsInteger = LL.getValueType().isInteger();
ISD::CondCode NewCC = ISD::getSetCCAndOperation(CC0, CC1, IsInteger);
if (NewCC != ISD::SETCC_INVALID &&
(!LegalOperations ||
(TLI.isCondCodeLegal(NewCC, LL.getSimpleValueType()) &&
TLI.isOperationLegal(ISD::SETCC, LL.getValueType())))) {
EVT CCVT = getSetCCResultType(LL.getValueType());
if (N0.getValueType() == CCVT ||
(!LegalOperations && N0.getValueType() == MVT::i1))
return DAG.getSetCC(DL, N0.getValueType(), LL, LR, NewCC);
TLI.isOperationLegal(ISD::SETCC, LLVT)))) {
EVT CCVT = getSetCCResultType(LLVT);
if (VT == CCVT || (!LegalOperations && VT == MVT::i1))
return DAG.getSetCC(DL, VT, LL, LR, NewCC);
}
}