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Add FastISel support for several more binary operators. 

llvm-svn: 55020
This commit is contained in:
Dan Gohman 2008-08-20 00:11:48 +00:00
parent 02d4a78688
commit a3e4d5a5e1
3 changed files with 101 additions and 18 deletions
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31
llvm/include/llvm/CodeGen/FastISel.h
View File

@ -50,22 +50,53 @@ protected:
virtual ~FastISel();
/// FastEmit_r - This method is called by target-independent code
/// to request that an instruction with the given type and opcode
/// be emitted.
virtual unsigned FastEmit_(MVT::SimpleValueType VT,
ISD::NodeType Opcode);
/// FastEmit_r - This method is called by target-independent code
/// to request that an instruction with the given type, opcode, and
/// register operand be emitted.
///
virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
ISD::NodeType Opcode, unsigned Op0);
/// FastEmit_rr - This method is called by target-independent code
/// to request that an instruction with the given type, opcode, and
/// register operands be emitted.
///
virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
ISD::NodeType Opcode,
unsigned Op0, unsigned Op1);
/// FastEmitInst_ - Emit a MachineInstr with no operands and a
/// result register in the given register class.
///
unsigned FastEmitInst_(unsigned MachineInstOpcode,
const TargetRegisterClass *RC);
/// FastEmitInst_ - Emit a MachineInstr with one register operand
/// and a result register in the given register class.
///
unsigned FastEmitInst_r(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
unsigned Op0);
/// FastEmitInst_ - Emit a MachineInstr with two register operands
/// and a result register in the given register class.
///
unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
unsigned Op0, unsigned Op1);
private:
bool SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
DenseMap<const Value*, unsigned> &ValueMap);
bool SelectGetElementPtr(Instruction *I,
DenseMap<const Value*, unsigned> &ValueMap);
};
}

78
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
View File

@ -18,6 +18,34 @@
#include "llvm/Target/TargetInstrInfo.h"
using namespace llvm;
/// SelectBinaryOp - Select and emit code for a binary operator instruction,
/// which has an opcode which directly corresponds to the given ISD opcode.
///
bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
DenseMap<const Value*, unsigned> &ValueMap) {
unsigned Op0 = ValueMap[I->getOperand(0)];
unsigned Op1 = ValueMap[I->getOperand(1)];
MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
if (VT == MVT::Other || !VT.isSimple())
// Unhandled type. Halt "fast" selection and bail.
return false;
unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), ISDOpcode, Op0, Op1);
if (ResultReg == 0)
// Target-specific code wasn't able to find a machine opcode for
// the given ISD opcode and type. Halt "fast" selection and bail.
return false;
ValueMap[I] = ResultReg;
return true;
}
bool FastISel::SelectGetElementPtr(Instruction *I,
DenseMap<const Value*, unsigned> &ValueMap) {
// TODO: implement me
return false;
}
BasicBlock::iterator
FastISel::SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End,
DenseMap<const Value*, unsigned> &ValueMap) {
@ -25,23 +53,41 @@ FastISel::SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator En
for (; I != End; ++I) {
switch (I->getOpcode()) {
case Instruction::Add: {
unsigned Op0 = ValueMap[I->getOperand(0)];
unsigned Op1 = ValueMap[I->getOperand(1)];
MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
if (VT == MVT::Other || !VT.isSimple()) {
// Unhandled type. Halt "fast" selection and bail.
return I;
}
unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), ISD::ADD, Op0, Op1);
if (ResultReg == 0) {
// Target-specific code wasn't able to find a machine opcode for
// the given ISD opcode and type. Halt "fast" selection and bail.
return I;
}
ValueMap[I] = ResultReg;
case Instruction::Add:
if (!SelectBinaryOp(I, ISD::ADD, ValueMap)) return I; break;
case Instruction::Sub:
if (!SelectBinaryOp(I, ISD::SUB, ValueMap)) return I; break;
case Instruction::Mul:
if (!SelectBinaryOp(I, ISD::MUL, ValueMap)) return I; break;
case Instruction::SDiv:
if (!SelectBinaryOp(I, ISD::SDIV, ValueMap)) return I; break;
case Instruction::UDiv:
if (!SelectBinaryOp(I, ISD::UDIV, ValueMap)) return I; break;
case Instruction::FDiv:
if (!SelectBinaryOp(I, ISD::FDIV, ValueMap)) return I; break;
case Instruction::SRem:
if (!SelectBinaryOp(I, ISD::SREM, ValueMap)) return I; break;
case Instruction::URem:
if (!SelectBinaryOp(I, ISD::UREM, ValueMap)) return I; break;
case Instruction::FRem:
if (!SelectBinaryOp(I, ISD::FREM, ValueMap)) return I; break;
case Instruction::Shl:
if (!SelectBinaryOp(I, ISD::SHL, ValueMap)) return I; break;
case Instruction::LShr:
if (!SelectBinaryOp(I, ISD::SRL, ValueMap)) return I; break;
case Instruction::AShr:
if (!SelectBinaryOp(I, ISD::SRA, ValueMap)) return I; break;
case Instruction::And:
if (!SelectBinaryOp(I, ISD::AND, ValueMap)) return I; break;
case Instruction::Or:
if (!SelectBinaryOp(I, ISD::OR, ValueMap)) return I; break;
case Instruction::Xor:
if (!SelectBinaryOp(I, ISD::XOR, ValueMap)) return I; break;
case Instruction::GetElementPtr:
if (!SelectGetElementPtr(I, ValueMap)) return I;
break;
}
case Instruction::Br: {
BranchInst *BI = cast<BranchInst>(I);

10
llvm/test/CodeGen/X86/fast-isel.ll
View File

@ -9,9 +9,15 @@ entry:
br label %fast
fast:
%t = add i32 %r, %s
%t0 = add i32 %r, %s
%t1 = mul i32 %t0, %s
%t2 = sub i32 %t1, %s
%t3 = and i32 %t2, %s
%t4 = or i32 %t3, %s
%t5 = xor i32 %t4, %s
br label %exit
exit:
ret i32 %t
ret i32 %t5
}