forked from OSchip/llvm-project
[PowerPC] Remove redundant CRSET/CRUNSET in custom lowering of known CR bit spills
We lower known CR bit spills (CRSET/CRUNSET) to load and spill the known value but forgot to remove the redundant spills. e.g., This sequence was used to spill a CRUNSET: crclr 4*cr5+lt mfocrf r3,4 rlwinm r3,r3,20,0,0 stw r3,132(r1) Custom lowering of known CR bit spills lower it to: crxor 4*cr5+lt, 4*cr5+lt, 4*cr5+lt li r3,0 stw r3,132(r1) crxor is redundant if there is no use of 4*cr5+lt so we should remove it Differential revision: https://reviews.llvm.org/D67722
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@ -3184,6 +3184,11 @@ def ADDIStocHA : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentr
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// the function label.
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def UpdateGBR : PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
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// Pseudo-instruction marked for deletion. When deleting the instruction would
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// cause iterator invalidation in MIR transformation passes, this pseudo can be
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// used instead. It will be removed unconditionally at pre-emit time (prior to
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// branch selection).
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def UNENCODED_NOP: PPCEmitTimePseudo<(outs), (ins), "#UNENCODED_NOP", []>;
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// Standard shifts. These are represented separately from the real shifts above
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// so that we can distinguish between shifts that allow 5-bit and 6-bit shift
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@ -163,8 +163,19 @@ namespace {
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}
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bool runOnMachineFunction(MachineFunction &MF) override {
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if (skipFunction(MF.getFunction()) || !RunPreEmitPeephole)
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if (skipFunction(MF.getFunction()) || !RunPreEmitPeephole) {
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// Remove UNENCODED_NOP even when this pass is disabled.
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// This needs to be done unconditionally so we don't emit zeros
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// in the instruction stream.
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SmallVector<MachineInstr *, 4> InstrsToErase;
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for (MachineBasicBlock &MBB : MF)
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for (MachineInstr &MI : MBB)
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if (MI.getOpcode() == PPC::UNENCODED_NOP)
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InstrsToErase.push_back(&MI);
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for (MachineInstr *MI : InstrsToErase)
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MI->eraseFromParent();
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return false;
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}
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bool Changed = false;
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const PPCInstrInfo *TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo();
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const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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@ -173,6 +184,10 @@ namespace {
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Changed |= removeRedundantLIs(MBB, TRI);
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for (MachineInstr &MI : MBB) {
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unsigned Opc = MI.getOpcode();
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if (Opc == PPC::UNENCODED_NOP) {
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InstrsToErase.push_back(&MI);
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continue;
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}
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// Detect self copies - these can result from running AADB.
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if (PPCInstrInfo::isSameClassPhysRegCopy(Opc)) {
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const MCInstrDesc &MCID = TII->get(Opc);
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@ -747,12 +747,18 @@ void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
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Register SrcReg = MI.getOperand(0).getReg();
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// Search up the BB to find the definition of the CR bit.
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MachineBasicBlock::reverse_iterator Ins;
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MachineBasicBlock::reverse_iterator Ins = MI;
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MachineBasicBlock::reverse_iterator Rend = MBB.rend();
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++Ins;
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unsigned CRBitSpillDistance = 0;
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for (Ins = MI; Ins != MBB.rend(); Ins++) {
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bool SeenUse = false;
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for (; Ins != Rend; ++Ins) {
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// Definition found.
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if (Ins->modifiesRegister(SrcReg, TRI))
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break;
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// Use found.
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if (Ins->readsRegister(SrcReg, TRI))
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SeenUse = true;
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// Unable to find CR bit definition within maximum search distance.
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if (CRBitSpillDistance == MaxCRBitSpillDist) {
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Ins = MI;
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@ -767,15 +773,18 @@ void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
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if (Ins == MBB.rend())
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Ins = MI;
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bool SpillsKnownBit = false;
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// There is no need to extract the CR bit if its value is already known.
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switch (Ins->getOpcode()) {
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case PPC::CRUNSET:
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BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LI8 : PPC::LI), Reg)
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.addImm(0);
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SpillsKnownBit = true;
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break;
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case PPC::CRSET:
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BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LIS8 : PPC::LIS), Reg)
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.addImm(-32768);
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SpillsKnownBit = true;
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break;
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default:
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// We need to move the CR field that contains the CR bit we are spilling.
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@ -803,8 +812,13 @@ void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
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.addReg(Reg, RegState::Kill),
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FrameIndex);
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bool KillsCRBit = MI.killsRegister(SrcReg, TRI);
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// Discard the pseudo instruction.
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MBB.erase(II);
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if (SpillsKnownBit && KillsCRBit && !SeenUse) {
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Ins->setDesc(TII.get(PPC::UNENCODED_NOP));
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Ins->RemoveOperand(0);
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}
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}
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void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II,
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@ -2,6 +2,9 @@
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -ppc-late-peephole=false \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s \
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; RUN: --implicit-check-not creqv --implicit-check-not crxor
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; For known CRBit spills, CRSET/CRUNSET, it is more efficient to just load and
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@ -21,7 +24,7 @@ define dso_local signext i32 @spillCRSET(i32 signext %p1, i32 signext %p2) {
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; CHECK-DAG: mfocrf [[REG2:.*]], [[CREG]]
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; CHECK-DAG: rlwinm [[REG2]], [[REG2]]
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; CHECK: .LBB0_3:
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; CHECK-DAG: creqv [[CREG:.*]]*cr5+lt, [[CREG]]*cr5+lt, [[CREG]]*cr5+lt
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; CHECK-NOT: #UNENCODED_NOP
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; CHECK: lis [[REG1:.*]], -32768
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; CHECK: .LBB0_4:
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; CHECK-NOT: mfocrf [[REG2:.*]], [[CREG]]
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@ -81,8 +84,8 @@ if.end13: ; preds = %if.then6, %for.end,
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define dso_local signext i32 @spillCRUNSET(%struct.p5rx* readonly %p1, i32 signext %p2, i32 signext %p3) {
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; CHECK-LABEL: spillCRUNSET:
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; CHECK: # %bb.0: # %entry
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; CHECK-DAG: crxor [[CREG:.*]]*cr5+lt, [[CREG]]*cr5+lt, [[CREG]]*cr5+lt
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; CHECK-DAG: li [[REG1:.*]], 0
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; CHECK-NOT: #UNENCODED_NOP
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; CHECK-NOT: mfocrf [[REG2:.*]], [[CREG]]
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; CHECK-NOT: rlwinm [[REG2]], [[REG2]]
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; CHECK: stw [[REG1]]
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