maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[Hexagon] Do not insert non-phis before phis in bit simplification 

llvm-svn: 257606
This commit is contained in:
Krzysztof Parzyszek 2016-01-13 15:48:18 +00:00
parent beb02b5b8f
commit a3c5d44437
2 changed files with 77 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
View File

@ -1275,6 +1275,8 @@ bool RedundantInstrElimination::processBlock(MachineBasicBlock &B,
if (!BT.has(RD.Reg))
continue;
const BitTracker::RegisterCell &DC = BT.lookup(RD.Reg);
auto At = MI->isPHI() ? B.getFirstNonPHI()
: MachineBasicBlock::iterator(MI);
// Find a source operand that is equal to the result.
for (auto &Op : MI->uses()) {
@ -1298,7 +1300,7 @@ bool RedundantInstrElimination::processBlock(MachineBasicBlock &B,
DebugLoc DL = MI->getDebugLoc();
const TargetRegisterClass *FRC = HBS::getFinalVRegClass(RD, MRI);
unsigned NewR = MRI.createVirtualRegister(FRC);
BuildMI(B, I, DL, HII.get(TargetOpcode::COPY), NewR)
BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
.addReg(RS.Reg, 0, RS.Sub);
HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI);
BT.put(BitTracker::RegisterRef(NewR), SC);
@ -1925,7 +1927,9 @@ bool BitSimplification::genPackhl(MachineInstr *MI,
MachineBasicBlock &B = *MI->getParent();
unsigned NewR = MRI.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
DebugLoc DL = MI->getDebugLoc();
BuildMI(B, MI, DL, HII.get(Hexagon::S2_packhl), NewR)
auto At = MI->isPHI() ? B.getFirstNonPHI()
: MachineBasicBlock::iterator(MI);
BuildMI(B, At, DL, HII.get(Hexagon::S2_packhl), NewR)
.addReg(Rs.Reg, 0, Rs.Sub)
.addReg(Rt.Reg, 0, Rt.Sub);
HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI);
@ -1950,9 +1954,11 @@ bool BitSimplification::genExtractHalf(MachineInstr *MI,
// Prefer zxth, since zxth can go in any slot, while extractu only in
// slots 2 and 3.
unsigned NewR = 0;
auto At = MI->isPHI() ? B.getFirstNonPHI()
: MachineBasicBlock::iterator(MI);
if (L.Low && Opc != Hexagon::A2_zxth) {
NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
BuildMI(B, MI, DL, HII.get(Hexagon::A2_zxth), NewR)
BuildMI(B, At, DL, HII.get(Hexagon::A2_zxth), NewR)
.addReg(L.Reg, 0, L.Sub);
} else if (!L.Low && Opc != Hexagon::S2_extractu) {
NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
@ -1989,7 +1995,9 @@ bool BitSimplification::genCombineHalf(MachineInstr *MI,
MachineBasicBlock &B = *MI->getParent();
DebugLoc DL = MI->getDebugLoc();
unsigned NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
BuildMI(B, MI, DL, HII.get(COpc), NewR)
auto At = MI->isPHI() ? B.getFirstNonPHI()
: MachineBasicBlock::iterator(MI);
BuildMI(B, At, DL, HII.get(COpc), NewR)
.addReg(H.Reg, 0, H.Sub)
.addReg(L.Reg, 0, L.Sub);
HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI);
@ -2043,7 +2051,9 @@ bool BitSimplification::genExtractLow(MachineInstr *MI,
continue;
unsigned NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
auto MIB = BuildMI(B, MI, DL, HII.get(NewOpc), NewR)
auto At = MI->isPHI() ? B.getFirstNonPHI()
: MachineBasicBlock::iterator(MI);
auto MIB = BuildMI(B, At, DL, HII.get(NewOpc), NewR)
.addReg(RS.Reg, 0, RS.Sub);
if (NewOpc == Hexagon::A2_andir)
MIB.addImm((1 << W) - 1);
@ -2076,6 +2086,8 @@ bool BitSimplification::simplifyTstbit(MachineInstr *MI,
if (!BT.has(RS.Reg) || !HBS::getSubregMask(RS, F, W, MRI))
return false;
MachineBasicBlock &B = *MI->getParent();
auto At = MI->isPHI() ? B.getFirstNonPHI()
: MachineBasicBlock::iterator(MI);
const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg);
const BitTracker::BitValue &V = SC[F+BN];
@ -2098,7 +2110,7 @@ bool BitSimplification::simplifyTstbit(MachineInstr *MI,
}
if (P != UINT_MAX) {
unsigned NewR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
BuildMI(B, MI, DL, HII.get(Hexagon::S2_tstbit_i), NewR)
BuildMI(B, At, DL, HII.get(Hexagon::S2_tstbit_i), NewR)
.addReg(RR.Reg, 0, RR.Sub)
.addImm(P);
HBS::replaceReg(RD.Reg, NewR, MRI);
@ -2108,7 +2120,7 @@ bool BitSimplification::simplifyTstbit(MachineInstr *MI,
} else if (V.is(0) || V.is(1)) {
unsigned NewR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
unsigned NewOpc = V.is(0) ? Hexagon::TFR_PdFalse : Hexagon::TFR_PdTrue;
BuildMI(B, MI, DL, HII.get(NewOpc), NewR);
BuildMI(B, At, DL, HII.get(NewOpc), NewR);
HBS::replaceReg(RD.Reg, NewR, MRI);
return true;
}

58
llvm/test/CodeGen/Hexagon/bit-phi.ll Normal file
View File

@ -0,0 +1,58 @@
; RUN: llc -march=hexagon < %s
; REQUIRES: asserts
target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
target triple = "hexagon-unknown--elf"
%struct.item = type { i32, i8*, i8*, i32, i8, i8, i16, i32, i8, i16, i32 }
declare %struct.item* @foo(%struct.item*, i8*, i32) #1
; Function Attrs: nounwind
define i32 @bar(%struct.item** %ptr, i8* %buf, i32 %c, i8* %d, i32 %e) #1 {
entry:
br i1 undef, label %return, label %if.end
if.end: ; preds = %entry
br i1 undef, label %while.cond13.preheader, label %if.end3
if.end3: ; preds = %if.end
br label %while.cond13.preheader
while.cond13.preheader: ; preds = %if.end3, %if.end
br i1 undef, label %while.body20, label %return
while.body20: ; preds = %if.end38, %while.cond13.preheader
%addr.0100 = phi i32 [ undef, %if.end38 ], [ %c, %while.cond13.preheader ]
%cond = select i1 undef, i32 %addr.0100, i32 undef
br i1 undef, label %while.body20.if.end38_crit_edge, label %if.then32
while.body20.if.end38_crit_edge: ; preds = %while.body20
%conv39.pre = and i32 %cond, 65535
br label %if.end38
if.then32: ; preds = %while.body20
%conv33 = and i32 %cond, 65535
%.pre = load %struct.item*, %struct.item** %ptr, align 4, !tbaa !1
br label %if.end38
if.end38: ; preds = %if.then32, %while.body20.if.end38_crit_edge
%conv39.pre-phi = phi i32 [ %conv39.pre, %while.body20.if.end38_crit_edge ], [ %conv33, %if.then32 ]
%0 = phi %struct.item* [ undef, %while.body20.if.end38_crit_edge ], [ %.pre, %if.then32 ]
%add = add i32 %conv39.pre-phi, 0
%call52 = tail call %struct.item* @foo(%struct.item* %0, i8* %d, i32 %e) #1
br i1 undef, label %while.body20, label %return
return: ; preds = %if.end38, %while.cond13.preheader, %entry
%retval.0 = phi i32 [ 0, %entry ], [ 0, %while.cond13.preheader ], [ %add, %if.end38 ]
ret i32 %retval.0
}
attributes #0 = { nounwind readonly }
attributes #1 = { nounwind }
!1 = !{!2, !2, i64 0}
!2 = !{!"any pointer", !3, i64 0}
!3 = !{!"omnipotent char", !4, i64 0}
!4 = !{!"Simple C/C++ TBAA"}