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Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it 

doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.

llvm-svn: 104203
This commit is contained in:
Dan Gohman 2010-05-20 01:23:41 +00:00
parent 87fe5d5618
commit a3b7570a3a
2 changed files with 5 additions and 1 deletions
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3
llvm/lib/Target/X86/X86InstrSSE.td
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@ -1102,7 +1102,8 @@ def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
}
// Load, store, and memory fence
def SFENCE : PSI<0xAE, MRM7r, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
TB, Requires<[HasSSE1]>;
// MXCSR register
def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),

3
llvm/test/MC/AsmParser/X86/x86_32-new-encoder.s
View File

@ -1,5 +1,8 @@
// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s
sfence
// CHECK: sfence
// CHECK: encoding: [0x0f,0xae,0xf8]
lfence
// CHECK: lfence
// CHECK: encoding: [0x0f,0xae,0xe8]