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AMDGPU: Fix disassembly of aperture registers 

llvm-svn: 295555
This commit is contained in:
Matt Arsenault 2017-02-18 18:41:41 +00:00
parent e823d92f7f
commit a3b3b489fb
2 changed files with 18 additions and 0 deletions
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5
llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
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@ -523,6 +523,11 @@ MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
case 124: return createRegOperand(M0);
case 126: return createRegOperand(EXEC_LO);
case 127: return createRegOperand(EXEC_HI);
case 235: return createRegOperand(SRC_SHARED_BASE);
case 236: return createRegOperand(SRC_SHARED_LIMIT);
case 237: return createRegOperand(SRC_PRIVATE_BASE);
case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
// TODO: SRC_POPS_EXITING_WAVE_ID
// ToDo: no support for vccz register
case 251: break;
// ToDo: no support for execz register

13
llvm/test/MC/Disassembler/AMDGPU/aperture-regs.ll Normal file
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@ -0,0 +1,13 @@
# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX9 %s
# GFX9: v_mov_b32_e32 v1, src_shared_base ; encoding: [0xeb,0x02,0x02,0x7e]
0xeb 0x02 0x02 0x7e
# GFX9: v_mov_b32_e32 v1, src_shared_limit ; encoding: [0xec,0x02,0x02,0x7e]
0xec 0x02 0x02 0x7e
# GFX9: v_mov_b32_e32 v1, src_private_base ; encoding: [0xed,0x02,0x02,0x7e]
0xed 0x02 0x02 0x7e
# GFX9: v_mov_b32_e32 v1, src_private_limit ; encoding: [0xee,0x02,0x02,0x7e]
0xee 0x02 0x02 0x7e