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[X86] Convert most remaining XOP uses of X86SchedWritePair scheduler classes to X86SchedWriteWidths. 

llvm-svn: 331369
This commit is contained in:
Simon Pilgrim 2018-05-02 16:25:41 +00:00
parent 2f4100f56e
commit a3a4df3708
1 changed files with 102 additions and 88 deletions
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190
llvm/lib/Target/X86/X86InstrXOP.td
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@ -18,7 +18,7 @@ multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int, PatFrag memop> {
def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
[(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP,
Sched<[WritePHAddLd, ReadAfterLd]>;
Sched<[WritePHAdd.Folded, ReadAfterLd]>;
}
let ExeDomain = SSEPackedInt in {
@ -41,119 +41,124 @@ let ExeDomain = SSEPackedInt in {
// Scalar load 2 addr operand instructions
multiclass xop2opsld<bits<8> opc, string OpcodeStr, Intrinsic Int,
Operand memop, ComplexPattern mem_cpat> {
Operand memop, ComplexPattern mem_cpat,
X86FoldableSchedWrite sched> {
def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
[(set VR128:$dst, (Int VR128:$src))]>, XOP, Sched<[WriteFAdd]>;
[(set VR128:$dst, (Int VR128:$src))]>, XOP, Sched<[sched]>;
def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src),
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
[(set VR128:$dst, (Int (bitconvert mem_cpat:$src)))]>, XOP,
Sched<[WriteFAddLd, ReadAfterLd]>;
Sched<[sched.Folded, ReadAfterLd]>;
}
multiclass xop2op128<bits<8> opc, string OpcodeStr, Intrinsic Int,
PatFrag memop> {
PatFrag memop, X86FoldableSchedWrite sched> {
def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
[(set VR128:$dst, (Int VR128:$src))]>, XOP, Sched<[WriteFAdd]>;
[(set VR128:$dst, (Int VR128:$src))]>, XOP, Sched<[sched]>;
def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
[(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP,
Sched<[WriteFAddLd, ReadAfterLd]>;
Sched<[sched.Folded, ReadAfterLd]>;
}
multiclass xop2op256<bits<8> opc, string OpcodeStr, Intrinsic Int,
PatFrag memop> {
PatFrag memop, X86FoldableSchedWrite sched> {
def Yrr : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
[(set VR256:$dst, (Int VR256:$src))]>, XOP, VEX_L, Sched<[WriteFAddY]>;
[(set VR256:$dst, (Int VR256:$src))]>, XOP, VEX_L, Sched<[sched]>;
def Yrm : IXOP<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
[(set VR256:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP, VEX_L,
Sched<[WriteFAddYLd, ReadAfterLd]>;
Sched<[sched.Folded, ReadAfterLd]>;
}
let ExeDomain = SSEPackedSingle in {
defm VFRCZSS : xop2opsld<0x82, "vfrczss", int_x86_xop_vfrcz_ss,
ssmem, sse_load_f32>;
defm VFRCZPS : xop2op128<0x80, "vfrczps", int_x86_xop_vfrcz_ps, loadv4f32>;
defm VFRCZPS : xop2op256<0x80, "vfrczps", int_x86_xop_vfrcz_ps_256, loadv8f32>;
ssmem, sse_load_f32, SchedWriteFAdd.XMM>;
defm VFRCZPS : xop2op128<0x80, "vfrczps", int_x86_xop_vfrcz_ps, loadv4f32,
SchedWriteFAdd.XMM>;
defm VFRCZPS : xop2op256<0x80, "vfrczps", int_x86_xop_vfrcz_ps_256, loadv8f32,
SchedWriteFAdd.YMM>;
}
let ExeDomain = SSEPackedDouble in {
defm VFRCZSD : xop2opsld<0x83, "vfrczsd", int_x86_xop_vfrcz_sd,
sdmem, sse_load_f64>;
defm VFRCZPD : xop2op128<0x81, "vfrczpd", int_x86_xop_vfrcz_pd, loadv2f64>;
defm VFRCZPD : xop2op256<0x81, "vfrczpd", int_x86_xop_vfrcz_pd_256, loadv4f64>;
sdmem, sse_load_f64, SchedWriteFAdd.XMM>;
defm VFRCZPD : xop2op128<0x81, "vfrczpd", int_x86_xop_vfrcz_pd, loadv2f64,
SchedWriteFAdd.XMM>;
defm VFRCZPD : xop2op256<0x81, "vfrczpd", int_x86_xop_vfrcz_pd_256, loadv4f64,
SchedWriteFAdd.YMM>;
}
multiclass xop3op<bits<8> opc, string OpcodeStr, SDNode OpNode,
ValueType vt128> {
ValueType vt128, X86FoldableSchedWrite sched> {
def rr : IXOP<opc, MRMSrcReg4VOp3, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set VR128:$dst,
(vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2))))]>,
XOP, Sched<[WriteVarVecShift]>;
XOP, Sched<[sched]>;
def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, i128mem:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set VR128:$dst,
(vt128 (OpNode (vt128 VR128:$src1),
(vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
XOP_4V, VEX_W, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
XOP_4V, VEX_W, Sched<[sched.Folded, ReadAfterLd]>;
def mr : IXOP<opc, MRMSrcMem4VOp3, (outs VR128:$dst),
(ins i128mem:$src1, VR128:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set VR128:$dst,
(vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))),
(vt128 VR128:$src2))))]>,
XOP, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
XOP, Sched<[sched.Folded, ReadAfterLd]>;
// For disassembler
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
def rr_REV : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[]>,
XOP_4V, VEX_W, Sched<[WriteVarVecShift]>, FoldGenData<NAME#rr>;
XOP_4V, VEX_W, Sched<[sched]>, FoldGenData<NAME#rr>;
}
let ExeDomain = SSEPackedInt in {
defm VPROTB : xop3op<0x90, "vprotb", rotl, v16i8>;
defm VPROTD : xop3op<0x92, "vprotd", rotl, v4i32>;
defm VPROTQ : xop3op<0x93, "vprotq", rotl, v2i64>;
defm VPROTW : xop3op<0x91, "vprotw", rotl, v8i16>;
defm VPSHAB : xop3op<0x98, "vpshab", X86vpsha, v16i8>;
defm VPSHAD : xop3op<0x9A, "vpshad", X86vpsha, v4i32>;
defm VPSHAQ : xop3op<0x9B, "vpshaq", X86vpsha, v2i64>;
defm VPSHAW : xop3op<0x99, "vpshaw", X86vpsha, v8i16>;
defm VPSHLB : xop3op<0x94, "vpshlb", X86vpshl, v16i8>;
defm VPSHLD : xop3op<0x96, "vpshld", X86vpshl, v4i32>;
defm VPSHLQ : xop3op<0x97, "vpshlq", X86vpshl, v2i64>;
defm VPSHLW : xop3op<0x95, "vpshlw", X86vpshl, v8i16>;
defm VPROTB : xop3op<0x90, "vprotb", rotl, v16i8, SchedWriteVarVecShift.XMM>;
defm VPROTD : xop3op<0x92, "vprotd", rotl, v4i32, SchedWriteVarVecShift.XMM>;
defm VPROTQ : xop3op<0x93, "vprotq", rotl, v2i64, SchedWriteVarVecShift.XMM>;
defm VPROTW : xop3op<0x91, "vprotw", rotl, v8i16, SchedWriteVarVecShift.XMM>;
defm VPSHAB : xop3op<0x98, "vpshab", X86vpsha, v16i8, SchedWriteVarVecShift.XMM>;
defm VPSHAD : xop3op<0x9A, "vpshad", X86vpsha, v4i32, SchedWriteVarVecShift.XMM>;
defm VPSHAQ : xop3op<0x9B, "vpshaq", X86vpsha, v2i64, SchedWriteVarVecShift.XMM>;
defm VPSHAW : xop3op<0x99, "vpshaw", X86vpsha, v8i16, SchedWriteVarVecShift.XMM>;
defm VPSHLB : xop3op<0x94, "vpshlb", X86vpshl, v16i8, SchedWriteVarVecShift.XMM>;
defm VPSHLD : xop3op<0x96, "vpshld", X86vpshl, v4i32, SchedWriteVarVecShift.XMM>;
defm VPSHLQ : xop3op<0x97, "vpshlq", X86vpshl, v2i64, SchedWriteVarVecShift.XMM>;
defm VPSHLW : xop3op<0x95, "vpshlw", X86vpshl, v8i16, SchedWriteVarVecShift.XMM>;
}
multiclass xop3opimm<bits<8> opc, string OpcodeStr, SDNode OpNode,
ValueType vt128> {
ValueType vt128, X86FoldableSchedWrite sched> {
def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, u8imm:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set VR128:$dst,
(vt128 (OpNode (vt128 VR128:$src1), imm:$src2)))]>,
XOP, Sched<[WriteVecShift]>;
XOP, Sched<[sched]>;
def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
(ins i128mem:$src1, u8imm:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set VR128:$dst,
(vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))), imm:$src2)))]>,
XOP, Sched<[WriteVecShiftLd, ReadAfterLd]>;
XOP, Sched<[sched.Folded, ReadAfterLd]>;
}
let ExeDomain = SSEPackedInt in {
defm VPROTB : xop3opimm<0xC0, "vprotb", X86vrotli, v16i8>;
defm VPROTD : xop3opimm<0xC2, "vprotd", X86vrotli, v4i32>;
defm VPROTQ : xop3opimm<0xC3, "vprotq", X86vrotli, v2i64>;
defm VPROTW : xop3opimm<0xC1, "vprotw", X86vrotli, v8i16>;
defm VPROTB : xop3opimm<0xC0, "vprotb", X86vrotli, v16i8, SchedWriteVecShift.XMM>;
defm VPROTD : xop3opimm<0xC2, "vprotd", X86vrotli, v4i32, SchedWriteVecShift.XMM>;
defm VPROTQ : xop3opimm<0xC3, "vprotq", X86vrotli, v2i64, SchedWriteVecShift.XMM>;
defm VPROTW : xop3opimm<0xC1, "vprotw", X86vrotli, v8i16, SchedWriteVecShift.XMM>;
}
// Instruction where second source can be memory, but third must be register
@ -178,29 +183,29 @@ multiclass xop4opm2<bits<8> opc, string OpcodeStr, Intrinsic Int,
let ExeDomain = SSEPackedInt in {
defm VPMADCSWD : xop4opm2<0xB6, "vpmadcswd",
int_x86_xop_vpmadcswd, WriteVecIMul>;
int_x86_xop_vpmadcswd, SchedWriteVecIMul.XMM>;
defm VPMADCSSWD : xop4opm2<0xA6, "vpmadcsswd",
int_x86_xop_vpmadcsswd, WriteVecIMul>;
int_x86_xop_vpmadcsswd, SchedWriteVecIMul.XMM>;
defm VPMACSWW : xop4opm2<0x95, "vpmacsww",
int_x86_xop_vpmacsww, WriteVecIMul>;
int_x86_xop_vpmacsww, SchedWriteVecIMul.XMM>;
defm VPMACSWD : xop4opm2<0x96, "vpmacswd",
int_x86_xop_vpmacswd, WriteVecIMul>;
int_x86_xop_vpmacswd, SchedWriteVecIMul.XMM>;
defm VPMACSSWW : xop4opm2<0x85, "vpmacssww",
int_x86_xop_vpmacssww, WriteVecIMul>;
int_x86_xop_vpmacssww, SchedWriteVecIMul.XMM>;
defm VPMACSSWD : xop4opm2<0x86, "vpmacsswd",
int_x86_xop_vpmacsswd, WriteVecIMul>;
int_x86_xop_vpmacsswd, SchedWriteVecIMul.XMM>;
defm VPMACSSDQL : xop4opm2<0x87, "vpmacssdql",
int_x86_xop_vpmacssdql, WritePMULLD>;
int_x86_xop_vpmacssdql, SchedWritePMULLD.XMM>;
defm VPMACSSDQH : xop4opm2<0x8F, "vpmacssdqh",
int_x86_xop_vpmacssdqh, WritePMULLD>;
int_x86_xop_vpmacssdqh, SchedWritePMULLD.XMM>;
defm VPMACSSDD : xop4opm2<0x8E, "vpmacssdd",
int_x86_xop_vpmacssdd, WritePMULLD>;
int_x86_xop_vpmacssdd, SchedWritePMULLD.XMM>;
defm VPMACSDQL : xop4opm2<0x97, "vpmacsdql",
int_x86_xop_vpmacsdql, WritePMULLD>;
int_x86_xop_vpmacsdql, SchedWritePMULLD.XMM>;
defm VPMACSDQH : xop4opm2<0x9F, "vpmacsdqh",
int_x86_xop_vpmacsdqh, WritePMULLD>;
int_x86_xop_vpmacsdqh, SchedWritePMULLD.XMM>;
defm VPMACSDD : xop4opm2<0x9E, "vpmacsdd",
int_x86_xop_vpmacsdd, WritePMULLD>;
int_x86_xop_vpmacsdd, SchedWritePMULLD.XMM>;
}
// IFMA patterns - for cases where we can safely ignore the overflow bits from
@ -233,7 +238,8 @@ def CommuteVPCOMCC : SDNodeXForm<imm, [{
}]>;
// Instruction where second source can be memory, third must be imm8
multiclass xopvpcom<bits<8> opc, string Suffix, SDNode OpNode, ValueType vt128> {
multiclass xopvpcom<bits<8> opc, string Suffix, SDNode OpNode, ValueType vt128,
X86FoldableSchedWrite sched> {
let ExeDomain = SSEPackedInt in { // SSE integer instructions
let isCommutable = 1 in
def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
@ -243,7 +249,7 @@ multiclass xopvpcom<bits<8> opc, string Suffix, SDNode OpNode, ValueType vt128>
[(set VR128:$dst,
(vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
imm:$cc)))]>,
XOP_4V, Sched<[WriteVecALU]>;
XOP_4V, Sched<[sched]>;
def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, i128mem:$src2, XOPCC:$cc),
!strconcat("vpcom${cc}", Suffix,
@ -252,19 +258,19 @@ multiclass xopvpcom<bits<8> opc, string Suffix, SDNode OpNode, ValueType vt128>
(vt128 (OpNode (vt128 VR128:$src1),
(vt128 (bitconvert (loadv2i64 addr:$src2))),
imm:$cc)))]>,
XOP_4V, Sched<[WriteVecALULd, ReadAfterLd]>;
XOP_4V, Sched<[sched.Folded, ReadAfterLd]>;
let isAsmParserOnly = 1, hasSideEffects = 0 in {
def ri_alt : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, u8imm:$src3),
!strconcat("vpcom", Suffix,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[]>, XOP_4V, Sched<[WriteVecALU]>;
[]>, XOP_4V, Sched<[sched]>;
let mayLoad = 1 in
def mi_alt : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, i128mem:$src2, u8imm:$src3),
!strconcat("vpcom", Suffix,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[]>, XOP_4V, Sched<[WriteVecALULd, ReadAfterLd]>;
[]>, XOP_4V, Sched<[sched.Folded, ReadAfterLd]>;
}
}
@ -274,17 +280,17 @@ multiclass xopvpcom<bits<8> opc, string Suffix, SDNode OpNode, ValueType vt128>
(CommuteVPCOMCC imm:$cc))>;
}
defm VPCOMB : xopvpcom<0xCC, "b", X86vpcom, v16i8>;
defm VPCOMW : xopvpcom<0xCD, "w", X86vpcom, v8i16>;
defm VPCOMD : xopvpcom<0xCE, "d", X86vpcom, v4i32>;
defm VPCOMQ : xopvpcom<0xCF, "q", X86vpcom, v2i64>;
defm VPCOMUB : xopvpcom<0xEC, "ub", X86vpcomu, v16i8>;
defm VPCOMUW : xopvpcom<0xED, "uw", X86vpcomu, v8i16>;
defm VPCOMUD : xopvpcom<0xEE, "ud", X86vpcomu, v4i32>;
defm VPCOMUQ : xopvpcom<0xEF, "uq", X86vpcomu, v2i64>;
defm VPCOMB : xopvpcom<0xCC, "b", X86vpcom, v16i8, SchedWriteVecALU.XMM>;
defm VPCOMW : xopvpcom<0xCD, "w", X86vpcom, v8i16, SchedWriteVecALU.XMM>;
defm VPCOMD : xopvpcom<0xCE, "d", X86vpcom, v4i32, SchedWriteVecALU.XMM>;
defm VPCOMQ : xopvpcom<0xCF, "q", X86vpcom, v2i64, SchedWriteVecALU.XMM>;
defm VPCOMUB : xopvpcom<0xEC, "ub", X86vpcomu, v16i8, SchedWriteVecALU.XMM>;
defm VPCOMUW : xopvpcom<0xED, "uw", X86vpcomu, v8i16, SchedWriteVecALU.XMM>;
defm VPCOMUD : xopvpcom<0xEE, "ud", X86vpcomu, v4i32, SchedWriteVecALU.XMM>;
defm VPCOMUQ : xopvpcom<0xEF, "uq", X86vpcomu, v2i64, SchedWriteVecALU.XMM>;
multiclass xop4op<bits<8> opc, string OpcodeStr, SDNode OpNode,
ValueType vt128> {
ValueType vt128, X86FoldableSchedWrite sched> {
def rrr : IXOPi8Reg<opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, VR128:$src3),
!strconcat(OpcodeStr,
@ -292,7 +298,7 @@ multiclass xop4op<bits<8> opc, string OpcodeStr, SDNode OpNode,
[(set VR128:$dst,
(vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
(vt128 VR128:$src3))))]>,
XOP_4V, Sched<[WriteVarShuffle]>;
XOP_4V, Sched<[sched]>;
def rrm : IXOPi8Reg<opc, MRMSrcMemOp4, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, i128mem:$src3),
!strconcat(OpcodeStr,
@ -300,7 +306,7 @@ multiclass xop4op<bits<8> opc, string OpcodeStr, SDNode OpNode,
[(set VR128:$dst,
(vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
(vt128 (bitconvert (loadv2i64 addr:$src3))))))]>,
XOP_4V, VEX_W, Sched<[WriteVarShuffleLd, ReadAfterLd, ReadAfterLd]>;
XOP_4V, VEX_W, Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>;
def rmr : IXOPi8Reg<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, i128mem:$src2, VR128:$src3),
!strconcat(OpcodeStr,
@ -308,7 +314,7 @@ multiclass xop4op<bits<8> opc, string OpcodeStr, SDNode OpNode,
[(set VR128:$dst,
(v16i8 (OpNode (vt128 VR128:$src1), (vt128 (bitconvert (loadv2i64 addr:$src2))),
(vt128 VR128:$src3))))]>,
XOP_4V, Sched<[WriteVarShuffleLd, ReadAfterLd,
XOP_4V, Sched<[sched.Folded, ReadAfterLd,
// 128mem:$src2
ReadDefault, ReadDefault, ReadDefault, ReadDefault,
ReadDefault,
@ -320,37 +326,39 @@ multiclass xop4op<bits<8> opc, string OpcodeStr, SDNode OpNode,
(ins VR128:$src1, VR128:$src2, VR128:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[]>, XOP_4V, VEX_W, Sched<[WriteVarShuffle]>, FoldGenData<NAME#rrr>;
[]>, XOP_4V, VEX_W, Sched<[sched]>, FoldGenData<NAME#rrr>;
}
let ExeDomain = SSEPackedInt in {
defm VPPERM : xop4op<0xA3, "vpperm", X86vpperm, v16i8>;
defm VPPERM : xop4op<0xA3, "vpperm", X86vpperm, v16i8,
SchedWriteVarShuffle.XMM>;
}
// Instruction where either second or third source can be memory
multiclass xop4op_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
X86MemOperand x86memop, ValueType VT> {
X86MemOperand x86memop, ValueType VT,
X86FoldableSchedWrite sched> {
def rrr : IXOPi8Reg<opc, MRMSrcReg, (outs RC:$dst),
(ins RC:$src1, RC:$src2, RC:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[(set RC:$dst, (VT (or (and RC:$src3, RC:$src1),
(X86andnp RC:$src3, RC:$src2))))]>, XOP_4V,
Sched<[WriteShuffle]>;
Sched<[sched]>;
def rrm : IXOPi8Reg<opc, MRMSrcMemOp4, (outs RC:$dst),
(ins RC:$src1, RC:$src2, x86memop:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[(set RC:$dst, (VT (or (and (load addr:$src3), RC:$src1),
(X86andnp (load addr:$src3), RC:$src2))))]>,
XOP_4V, VEX_W, Sched<[WriteShuffleLd, ReadAfterLd, ReadAfterLd]>;
XOP_4V, VEX_W, Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>;
def rmr : IXOPi8Reg<opc, MRMSrcMem, (outs RC:$dst),
(ins RC:$src1, x86memop:$src2, RC:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[(set RC:$dst, (VT (or (and RC:$src3, RC:$src1),
(X86andnp RC:$src3, (load addr:$src2)))))]>,
XOP_4V, Sched<[WriteShuffleLd, ReadAfterLd,
XOP_4V, Sched<[sched.Folded, ReadAfterLd,
// x86memop:$src2
ReadDefault, ReadDefault, ReadDefault, ReadDefault,
ReadDefault,
@ -362,25 +370,27 @@ multiclass xop4op_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
(ins RC:$src1, RC:$src2, RC:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[]>, XOP_4V, VEX_W, Sched<[WriteShuffle]>, FoldGenData<NAME#rrr>;
[]>, XOP_4V, VEX_W, Sched<[sched]>, FoldGenData<NAME#rrr>;
}
let ExeDomain = SSEPackedInt in {
defm VPCMOV : xop4op_int<0xA2, "vpcmov", VR128, i128mem, v2i64>;
defm VPCMOVY : xop4op_int<0xA2, "vpcmov", VR256, i256mem, v4i64>, VEX_L;
defm VPCMOV : xop4op_int<0xA2, "vpcmov", VR128, i128mem, v2i64,
SchedWriteShuffle.XMM>;
defm VPCMOVY : xop4op_int<0xA2, "vpcmov", VR256, i256mem, v4i64,
SchedWriteShuffle.YMM>, VEX_L;
}
multiclass xop_vpermil2<bits<8> Opc, string OpcodeStr, RegisterClass RC,
X86MemOperand intmemop, X86MemOperand fpmemop,
ValueType VT, PatFrag FPLdFrag,
PatFrag IntLdFrag> {
ValueType VT, PatFrag FPLdFrag, PatFrag IntLdFrag,
X86FoldableSchedWrite sched> {
def rr : IXOP5<Opc, MRMSrcReg, (outs RC:$dst),
(ins RC:$src1, RC:$src2, RC:$src3, u8imm:$src4),
!strconcat(OpcodeStr,
"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
[(set RC:$dst,
(VT (X86vpermil2 RC:$src1, RC:$src2, RC:$src3, (i8 imm:$src4))))]>,
Sched<[WriteFVarShuffle]>;
Sched<[sched]>;
def rm : IXOP5<Opc, MRMSrcMemOp4, (outs RC:$dst),
(ins RC:$src1, RC:$src2, intmemop:$src3, u8imm:$src4),
!strconcat(OpcodeStr,
@ -389,7 +399,7 @@ multiclass xop_vpermil2<bits<8> Opc, string OpcodeStr, RegisterClass RC,
(VT (X86vpermil2 RC:$src1, RC:$src2,
(bitconvert (IntLdFrag addr:$src3)),
(i8 imm:$src4))))]>, VEX_W,
Sched<[WriteFVarShuffleLd, ReadAfterLd, ReadAfterLd]>;
Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>;
def mr : IXOP5<Opc, MRMSrcMem, (outs RC:$dst),
(ins RC:$src1, fpmemop:$src2, RC:$src3, u8imm:$src4),
!strconcat(OpcodeStr,
@ -397,7 +407,7 @@ multiclass xop_vpermil2<bits<8> Opc, string OpcodeStr, RegisterClass RC,
[(set RC:$dst,
(VT (X86vpermil2 RC:$src1, (FPLdFrag addr:$src2),
RC:$src3, (i8 imm:$src4))))]>,
Sched<[WriteFVarShuffleLd, ReadAfterLd,
Sched<[sched.Folded, ReadAfterLd,
// fpmemop:$src2
ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault,
// RC:$src3
@ -408,20 +418,24 @@ multiclass xop_vpermil2<bits<8> Opc, string OpcodeStr, RegisterClass RC,
(ins RC:$src1, RC:$src2, RC:$src3, u8imm:$src4),
!strconcat(OpcodeStr,
"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
[]>, VEX_W, Sched<[WriteFVarShuffle]>, FoldGenData<NAME#rr>;
[]>, VEX_W, Sched<[sched]>, FoldGenData<NAME#rr>;
}
let ExeDomain = SSEPackedDouble in {
defm VPERMIL2PD : xop_vpermil2<0x49, "vpermil2pd", VR128, i128mem, f128mem,
v2f64, loadv2f64, loadv2i64>;
v2f64, loadv2f64, loadv2i64,
SchedWriteFVarShuffle.XMM>;
defm VPERMIL2PDY : xop_vpermil2<0x49, "vpermil2pd", VR256, i256mem, f256mem,
v4f64, loadv4f64, loadv4i64>, VEX_L;
v4f64, loadv4f64, loadv4i64,
SchedWriteFVarShuffle.YMM>, VEX_L;
}
let ExeDomain = SSEPackedSingle in {
defm VPERMIL2PS : xop_vpermil2<0x48, "vpermil2ps", VR128, i128mem, f128mem,
v4f32, loadv4f32, loadv2i64>;
v4f32, loadv4f32, loadv2i64,
SchedWriteFVarShuffle.XMM>;
defm VPERMIL2PSY : xop_vpermil2<0x48, "vpermil2ps", VR256, i256mem, f256mem,
v8f32, loadv8f32, loadv4i64>, VEX_L;
v8f32, loadv8f32, loadv4i64,
SchedWriteFVarShuffle.YMM>, VEX_L;
}