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ARM Encoding information for UXTAH and friends. 

llvm-svn: 119753
This commit is contained in:
Jim Grosbach 2010-11-18 23:24:22 +00:00
parent 148d113e55
commit a391c97bd0
1 changed files with 12 additions and 0 deletions
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12
llvm/lib/Target/ARM/ARMInstrInfo.td
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@ -752,7 +752,14 @@ multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
[(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
Requires<[IsARM, HasV6]> {
bits<4> Rd;
bits<4> Rm;
bits<4> Rn;
let Inst{19-16} = Rn;
let Inst{15-12} = Rd;
let Inst{11-10} = 0b00;
let Inst{9-4} = 0b000111;
let Inst{3-0} = Rm;
}
def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
rot_imm:$rot),
@ -760,10 +767,15 @@ multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
[(set GPR:$Rd, (opnode GPR:$Rn,
(rotr GPR:$Rm, rot_imm:$rot)))]>,
Requires<[IsARM, HasV6]> {
bits<4> Rd;
bits<4> Rm;
bits<4> Rn;
bits<2> rot;
let Inst{19-16} = Rn;
let Inst{15-12} = Rd;
let Inst{11-10} = rot;
let Inst{9-4} = 0b000111;
let Inst{3-0} = Rm;
}
}