forked from OSchip/llvm-project
[CGP] auto-generate complete checks for add overflow tests; NFC
llvm-svn: 352437
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@ -4,45 +4,61 @@
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-apple-darwin10.0.0"
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; CHECK-LABEL: @test1(
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; CHECK: llvm.uadd.with.overflow
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; CHECK: ret i64
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define i64 @test1(i64 %a, i64 %b) nounwind ssp {
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entry:
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: [[UADD_OVERFLOW:%.*]] = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 [[B:%.*]], i64 [[A:%.*]])
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; CHECK-NEXT: [[UADD:%.*]] = extractvalue { i64, i1 } [[UADD_OVERFLOW]], 0
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; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i64, i1 } [[UADD_OVERFLOW]], 1
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; CHECK-NEXT: [[Q:%.*]] = select i1 [[OVERFLOW]], i64 [[B]], i64 42
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; CHECK-NEXT: ret i64 [[Q]]
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;
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%add = add i64 %b, %a
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%cmp = icmp ult i64 %add, %a
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%Q = select i1 %cmp, i64 %b, i64 42
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ret i64 %Q
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}
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; CHECK-LABEL: @test2(
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; CHECK: llvm.uadd.with.overflow
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; CHECK: ret i64
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define i64 @test2(i64 %a, i64 %b) nounwind ssp {
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entry:
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: [[UADD_OVERFLOW:%.*]] = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 [[B:%.*]], i64 [[A:%.*]])
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; CHECK-NEXT: [[UADD:%.*]] = extractvalue { i64, i1 } [[UADD_OVERFLOW]], 0
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; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i64, i1 } [[UADD_OVERFLOW]], 1
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; CHECK-NEXT: [[Q:%.*]] = select i1 [[OVERFLOW]], i64 [[B]], i64 42
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; CHECK-NEXT: ret i64 [[Q]]
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;
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%add = add i64 %b, %a
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%cmp = icmp ult i64 %add, %b
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%Q = select i1 %cmp, i64 %b, i64 42
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ret i64 %Q
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}
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; CHECK-LABEL: @test3(
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; CHECK: llvm.uadd.with.overflow
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; CHECK: ret i64
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define i64 @test3(i64 %a, i64 %b) nounwind ssp {
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entry:
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; CHECK-LABEL: @test3(
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; CHECK-NEXT: [[UADD_OVERFLOW:%.*]] = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 [[B:%.*]], i64 [[A:%.*]])
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; CHECK-NEXT: [[UADD:%.*]] = extractvalue { i64, i1 } [[UADD_OVERFLOW]], 0
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; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i64, i1 } [[UADD_OVERFLOW]], 1
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; CHECK-NEXT: [[Q:%.*]] = select i1 [[OVERFLOW]], i64 [[B]], i64 42
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; CHECK-NEXT: ret i64 [[Q]]
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;
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%add = add i64 %b, %a
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%cmp = icmp ugt i64 %b, %add
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%Q = select i1 %cmp, i64 %b, i64 42
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ret i64 %Q
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}
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; CHECK-LABEL: @test4(
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; CHECK: llvm.uadd.with.overflow
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; CHECK: extractvalue
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; CHECK: extractvalue
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; CHECK: select
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define i64 @test4(i64 %a, i64 %b, i1 %c) nounwind ssp {
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; CHECK-LABEL: @test4(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 [[C:%.*]], label [[NEXT:%.*]], label [[EXIT:%.*]]
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; CHECK: next:
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; CHECK-NEXT: [[UADD_OVERFLOW:%.*]] = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 [[B:%.*]], i64 [[A:%.*]])
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; CHECK-NEXT: [[UADD:%.*]] = extractvalue { i64, i1 } [[UADD_OVERFLOW]], 0
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; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i64, i1 } [[UADD_OVERFLOW]], 1
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; CHECK-NEXT: [[Q:%.*]] = select i1 [[OVERFLOW]], i64 [[B]], i64 42
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; CHECK-NEXT: ret i64 [[Q]]
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; CHECK: exit:
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; CHECK-NEXT: ret i64 0
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;
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entry:
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%add = add i64 %b, %a
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%cmp = icmp ugt i64 %b, %add
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@ -56,10 +72,19 @@ entry:
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ret i64 0
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}
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; CHECK-LABEL: @test5(
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; CHECK-NOT: llvm.uadd.with.overflow
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; CHECK: next
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define i64 @test5(i64 %a, i64 %b, i64* %ptr, i1 %c) nounwind ssp {
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; CHECK-LABEL: @test5(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[ADD:%.*]] = add i64 [[B:%.*]], [[A:%.*]]
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; CHECK-NEXT: store i64 [[ADD]], i64* [[PTR:%.*]]
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; CHECK-NEXT: br i1 [[C:%.*]], label [[NEXT:%.*]], label [[EXIT:%.*]]
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; CHECK: next:
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; CHECK-NEXT: [[TMP0:%.*]] = icmp ugt i64 [[B]], [[ADD]]
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; CHECK-NEXT: [[Q:%.*]] = select i1 [[TMP0]], i64 [[B]], i64 42
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; CHECK-NEXT: ret i64 [[Q]]
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; CHECK: exit:
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; CHECK-NEXT: ret i64 0
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;
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entry:
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%add = add i64 %b, %a
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store i64 %add, i64* %ptr
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@ -76,3 +101,4 @@ entry:
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; Check that every instruction inserted by -codegenprepare has a debug location.
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; DEBUG: CheckModuleDebugify: PASS
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