forked from OSchip/llvm-project
[InstCombine] add tests for (i32 X s>> 31) & Y; NFC
Also regenerate some check lines to more accurately show current transforms via name changes.
This commit is contained in:
Sanjay Patel
parent
c060c634ef
commit
a35673f4cf
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@ -1400,3 +1400,62 @@ define <2 x i8> @flip_masked_bit_nonuniform(<2 x i8> %A) {
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%C = and <2 x i8> %B, <i8 16, i8 4>
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ret <2 x i8> %C
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}
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define i8 @ashr_bitwidth_mask(i8 %x, i8 %y) {
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; CHECK-LABEL: @ashr_bitwidth_mask(
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; CHECK-NEXT: [[SIGN:%.*]] = ashr i8 [[X:%.*]], 7
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; CHECK-NEXT: [[NEG_OR_ZERO:%.*]] = and i8 [[SIGN]], [[Y:%.*]]
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; CHECK-NEXT: ret i8 [[NEG_OR_ZERO]]
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;
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%sign = ashr i8 %x, 7
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%neg_or_zero = and i8 %sign, %y
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ret i8 %neg_or_zero
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}
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define <2 x i8> @ashr_bitwidth_mask_vec_commute(<2 x i8> %x, <2 x i8> %py) {
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; CHECK-LABEL: @ashr_bitwidth_mask_vec_commute(
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; CHECK-NEXT: [[Y:%.*]] = mul <2 x i8> [[PY:%.*]], <i8 42, i8 2>
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; CHECK-NEXT: [[SIGN:%.*]] = ashr <2 x i8> [[X:%.*]], <i8 7, i8 7>
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; CHECK-NEXT: [[NEG_OR_ZERO:%.*]] = and <2 x i8> [[Y]], [[SIGN]]
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; CHECK-NEXT: ret <2 x i8> [[NEG_OR_ZERO]]
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;
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%y = mul <2 x i8> %py, <i8 42, i8 2> ; thwart complexity-based ordering
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%sign = ashr <2 x i8> %x, <i8 7, i8 7>
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%neg_or_zero = and <2 x i8> %y, %sign
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ret <2 x i8> %neg_or_zero
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}
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define i8 @ashr_bitwidth_mask_use(i8 %x, i8 %y) {
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; CHECK-LABEL: @ashr_bitwidth_mask_use(
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; CHECK-NEXT: [[SIGN:%.*]] = ashr i8 [[X:%.*]], 7
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; CHECK-NEXT: call void @use8(i8 [[SIGN]])
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; CHECK-NEXT: [[R:%.*]] = and i8 [[SIGN]], [[Y:%.*]]
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; CHECK-NEXT: ret i8 [[R]]
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;
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%sign = ashr i8 %x, 7
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call void @use8(i8 %sign)
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%r = and i8 %sign, %y
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ret i8 %r
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}
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define i8 @ashr_not_bitwidth_mask(i8 %x, i8 %y) {
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; CHECK-LABEL: @ashr_not_bitwidth_mask(
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; CHECK-NEXT: [[SIGN:%.*]] = ashr i8 [[X:%.*]], 6
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; CHECK-NEXT: [[R:%.*]] = and i8 [[SIGN]], [[Y:%.*]]
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; CHECK-NEXT: ret i8 [[R]]
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;
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%sign = ashr i8 %x, 6
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%r = and i8 %sign, %y
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ret i8 %r
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}
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define i8 @lshr_bitwidth_mask(i8 %x, i8 %y) {
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; CHECK-LABEL: @lshr_bitwidth_mask(
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; CHECK-NEXT: [[SIGN:%.*]] = lshr i8 [[X:%.*]], 7
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; CHECK-NEXT: [[R:%.*]] = and i8 [[SIGN]], [[Y:%.*]]
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; CHECK-NEXT: ret i8 [[R]]
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;
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%sign = lshr i8 %x, 7
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%r = and i8 %sign, %y
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ret i8 %r
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}
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@ -676,8 +676,8 @@ define i1 @test37_extra_uses(i32 %x, i32 %y, i32 %z) {
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define i32 @neg_max_s32(i32 %x, i32 %y) {
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; CHECK-LABEL: @neg_max_s32(
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; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[S_V:%.*]] = select i1 [[C]], i32 [[Y]], i32 [[X]]
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; CHECK-NEXT: ret i32 [[S_V]]
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; CHECK-NEXT: [[S_NEG:%.*]] = select i1 [[C]], i32 [[Y]], i32 [[X]]
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; CHECK-NEXT: ret i32 [[S_NEG]]
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;
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%nx = sub nsw i32 0, %x
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%ny = sub nsw i32 0, %y
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@ -690,8 +690,8 @@ define i32 @neg_max_s32(i32 %x, i32 %y) {
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define <4 x i32> @neg_max_v4s32(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: @neg_max_v4s32(
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; CHECK-NEXT: [[C:%.*]] = icmp sgt <4 x i32> [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[S_V:%.*]] = select <4 x i1> [[C]], <4 x i32> [[X]], <4 x i32> [[Y]]
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; CHECK-NEXT: ret <4 x i32> [[S_V]]
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; CHECK-NEXT: [[S_NEG:%.*]] = select <4 x i1> [[C]], <4 x i32> [[X]], <4 x i32> [[Y]]
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; CHECK-NEXT: ret <4 x i32> [[S_NEG]]
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;
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%nx = sub nsw <4 x i32> zeroinitializer, %x
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%ny = sub nsw <4 x i32> zeroinitializer, %y
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@ -985,8 +985,8 @@ define <2 x i32> @mulsub2_vec_nonuniform_undef(<2 x i32> %a0) {
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define i32 @muladd2(i32 %a0) {
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; CHECK-LABEL: @muladd2(
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; CHECK-NEXT: [[ADD_NEG_NEG:%.*]] = mul i32 [[A0:%.*]], -4
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; CHECK-NEXT: [[MUL:%.*]] = add i32 [[ADD_NEG_NEG]], -64
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; CHECK-NEXT: [[DOTNEG:%.*]] = mul i32 [[A0:%.*]], -4
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; CHECK-NEXT: [[MUL:%.*]] = add i32 [[DOTNEG]], -64
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; CHECK-NEXT: ret i32 [[MUL]]
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;
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%add = add i32 %a0, 16
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@ -996,8 +996,8 @@ define i32 @muladd2(i32 %a0) {
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define <2 x i32> @muladd2_vec(<2 x i32> %a0) {
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; CHECK-LABEL: @muladd2_vec(
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; CHECK-NEXT: [[ADD_NEG_NEG:%.*]] = mul <2 x i32> [[A0:%.*]], <i32 -4, i32 -4>
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; CHECK-NEXT: [[MUL:%.*]] = add <2 x i32> [[ADD_NEG_NEG]], <i32 -64, i32 -64>
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; CHECK-NEXT: [[DOTNEG:%.*]] = mul <2 x i32> [[A0:%.*]], <i32 -4, i32 -4>
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; CHECK-NEXT: [[MUL:%.*]] = add <2 x i32> [[DOTNEG]], <i32 -64, i32 -64>
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; CHECK-NEXT: ret <2 x i32> [[MUL]]
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;
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%add = add <2 x i32> %a0, <i32 16, i32 16>
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@ -1055,8 +1055,8 @@ define <2 x i32> @mulsub2_vec_nonuniform_undef(<2 x i32> %a0) {
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define i32 @muladd2(i32 %a0) {
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; CHECK-LABEL: @muladd2(
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; CHECK-NEXT: [[ADD_NEG_NEG:%.*]] = mul i32 [[A0:%.*]], -4
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; CHECK-NEXT: [[MUL:%.*]] = add i32 [[ADD_NEG_NEG]], -64
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; CHECK-NEXT: [[DOTNEG:%.*]] = mul i32 [[A0:%.*]], -4
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; CHECK-NEXT: [[MUL:%.*]] = add i32 [[DOTNEG]], -64
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; CHECK-NEXT: ret i32 [[MUL]]
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;
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%add = add i32 %a0, 16
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@ -1066,8 +1066,8 @@ define i32 @muladd2(i32 %a0) {
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define <2 x i32> @muladd2_vec(<2 x i32> %a0) {
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; CHECK-LABEL: @muladd2_vec(
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; CHECK-NEXT: [[ADD_NEG_NEG:%.*]] = mul <2 x i32> [[A0:%.*]], <i32 -4, i32 -4>
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; CHECK-NEXT: [[MUL:%.*]] = add <2 x i32> [[ADD_NEG_NEG]], <i32 -64, i32 -64>
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; CHECK-NEXT: [[DOTNEG:%.*]] = mul <2 x i32> [[A0:%.*]], <i32 -4, i32 -4>
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; CHECK-NEXT: [[MUL:%.*]] = add <2 x i32> [[DOTNEG]], <i32 -64, i32 -64>
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; CHECK-NEXT: ret <2 x i32> [[MUL]]
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;
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%add = add <2 x i32> %a0, <i32 16, i32 16>
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