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[X86] Use timm in MMX pinsrw/pextrw isel patterns. Add missing test cases. 

This fixes an isel failure after r372338.

llvm-svn: 372371
This commit is contained in:
Craig Topper 2019-09-20 06:00:35 +00:00
parent c768ad94b7
commit a34f13f2ba
2 changed files with 68 additions and 3 deletions
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6
llvm/lib/Target/X86/X86InstrMMX.td
View File

@ -535,7 +535,7 @@ def MMX_PEXTRWrr: MMXIi8<0xC5, MRMSrcReg,
(outs GR32orGR64:$dst), (ins VR64:$src1, i32u8imm:$src2),
"pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
[(set GR32orGR64:$dst, (int_x86_mmx_pextr_w VR64:$src1,
imm:$src2))]>,
timm:$src2))]>,
Sched<[WriteVecExtract]>;
let Constraints = "$src1 = $dst" in {
let Predicates = [HasMMX, HasSSE1] in {
@ -544,7 +544,7 @@ let Predicates = [HasMMX, HasSSE1] in {
(ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3),
"pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
GR32orGR64:$src2, imm:$src3))]>,
GR32orGR64:$src2, timm:$src3))]>,
Sched<[WriteVecInsert, ReadDefault, ReadInt2Fpu]>;
def MMX_PINSRWrm : MMXIi8<0xC4, MRMSrcMem,
@ -553,7 +553,7 @@ let Predicates = [HasMMX, HasSSE1] in {
"pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
(i32 (anyext (loadi16 addr:$src2))),
imm:$src3))]>,
timm:$src3))]>,
Sched<[WriteVecInsert.Folded, WriteVecInsert.ReadAfterFold]>;
}
}

65
llvm/test/CodeGen/X86/mmx-intrinsics.ll
View File

@ -1453,3 +1453,68 @@ define void @test90() {
}
declare void @llvm.x86.mmx.emms()
define <1 x i64> @test_mm_insert_pi16(<1 x i64> %a.coerce, i32 %d) nounwind {
; X86-LABEL: test_mm_insert_pi16:
; X86: # %bb.0: # %entry
; X86-NEXT: pushl %ebp
; X86-NEXT: movl %esp, %ebp
; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $16, %esp
; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: movl 12(%ebp), %ecx
; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0
; X86-NEXT: pinsrw $2, 16(%ebp), %mm0
; X86-NEXT: movq %mm0, (%esp)
; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp
; X86-NEXT: retl
;
; X64-LABEL: test_mm_insert_pi16:
; X64: # %bb.0: # %entry
; X64-NEXT: movq %rdi, %mm0
; X64-NEXT: pinsrw $2, %esi, %mm0
; X64-NEXT: movq %mm0, %rax
; X64-NEXT: retq
entry:
%0 = bitcast <1 x i64> %a.coerce to x86_mmx
%1 = tail call x86_mmx @llvm.x86.mmx.pinsr.w(x86_mmx %0, i32 %d, i32 2)
%2 = bitcast x86_mmx %1 to <1 x i64>
ret <1 x i64> %2
}
declare x86_mmx @llvm.x86.mmx.pinsr.w(x86_mmx, i32, i32 immarg)
define i32 @test_mm_extract_pi16(<1 x i64> %a.coerce) nounwind {
; X86-LABEL: test_mm_extract_pi16:
; X86: # %bb.0: # %entry
; X86-NEXT: pushl %ebp
; X86-NEXT: movl %esp, %ebp
; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $8, %esp
; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: movl 12(%ebp), %ecx
; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X86-NEXT: movl %eax, (%esp)
; X86-NEXT: movq (%esp), %mm0
; X86-NEXT: pextrw $2, %mm0, %eax
; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp
; X86-NEXT: retl
;
; X64-LABEL: test_mm_extract_pi16:
; X64: # %bb.0: # %entry
; X64-NEXT: movq %rdi, %mm0
; X64-NEXT: pextrw $2, %mm0, %eax
; X64-NEXT: retq
entry:
%0 = bitcast <1 x i64> %a.coerce to x86_mmx
%1 = tail call i32 @llvm.x86.mmx.pextr.w(x86_mmx %0, i32 2)
ret i32 %1
}
declare i32 @llvm.x86.mmx.pextr.w(x86_mmx, i32 immarg)