forked from OSchip/llvm-project
Change the 'isStore' inferrer to look for 'SDNPMayStore'
instead of "ISD::STORE". This allows us to mark target-specific dag nodes as storing (such as ppc byteswap stores). This allows us to remove more explicit isStore flags from the .td files. Finally, add a warning for when a .td file contains an explicit isStore and tblgen is able to infer it. llvm-svn: 45654
This commit is contained in:
Chris Lattner
parent
f4d55ec4e8
commit
a348f55ec6
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@ -38,10 +38,9 @@ class InstAlpha<bits<6> op, string asmstr, InstrItinClass itin> : Instruction {
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//3.3.1
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class MForm<bits<6> opcode, bit store, bit load, string asmstr, list<dag> pattern, InstrItinClass itin>
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class MForm<bits<6> opcode, bit load, string asmstr, list<dag> pattern, InstrItinClass itin>
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: InstAlpha<opcode, asmstr, itin> {
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let Pattern = pattern;
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let isStore = store;
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let isLoad = load;
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let Defs = [R28]; //We may use this for frame index calculations, so reserve it here
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@ -412,78 +412,78 @@ def JSR_COROUTINE : MbrForm< 0x1A, 0x03, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP),
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let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in {
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def LDQ : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)",
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def LDQ : MForm<0x29, 1, "ldq $RA,$DISP($RB)",
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[(set GPRC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_ild>;
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def LDQr : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!gprellow",
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def LDQr : MForm<0x29, 1, "ldq $RA,$DISP($RB)\t\t!gprellow",
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[(set GPRC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
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def LDL : MForm<0x28, 0, 1, "ldl $RA,$DISP($RB)",
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def LDL : MForm<0x28, 1, "ldl $RA,$DISP($RB)",
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[(set GPRC:$RA, (sextloadi32 (add GPRC:$RB, immSExt16:$DISP)))], s_ild>;
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def LDLr : MForm<0x28, 0, 1, "ldl $RA,$DISP($RB)\t\t!gprellow",
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def LDLr : MForm<0x28, 1, "ldl $RA,$DISP($RB)\t\t!gprellow",
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[(set GPRC:$RA, (sextloadi32 (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
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def LDBU : MForm<0x0A, 0, 1, "ldbu $RA,$DISP($RB)",
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def LDBU : MForm<0x0A, 1, "ldbu $RA,$DISP($RB)",
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[(set GPRC:$RA, (zextloadi8 (add GPRC:$RB, immSExt16:$DISP)))], s_ild>;
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def LDBUr : MForm<0x0A, 0, 1, "ldbu $RA,$DISP($RB)\t\t!gprellow",
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def LDBUr : MForm<0x0A, 1, "ldbu $RA,$DISP($RB)\t\t!gprellow",
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[(set GPRC:$RA, (zextloadi8 (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
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def LDWU : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)",
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def LDWU : MForm<0x0C, 1, "ldwu $RA,$DISP($RB)",
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[(set GPRC:$RA, (zextloadi16 (add GPRC:$RB, immSExt16:$DISP)))], s_ild>;
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def LDWUr : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)\t\t!gprellow",
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def LDWUr : MForm<0x0C, 1, "ldwu $RA,$DISP($RB)\t\t!gprellow",
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[(set GPRC:$RA, (zextloadi16 (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
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}
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let OutOperandList = (ops), InOperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in {
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def STB : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)",
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def STB : MForm<0x0E, 0, "stb $RA,$DISP($RB)",
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[(truncstorei8 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
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def STBr : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)\t\t!gprellow",
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def STBr : MForm<0x0E, 0, "stb $RA,$DISP($RB)\t\t!gprellow",
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[(truncstorei8 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
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def STW : MForm<0x0D, 1, 0, "stw $RA,$DISP($RB)",
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def STW : MForm<0x0D, 0, "stw $RA,$DISP($RB)",
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[(truncstorei16 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
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def STWr : MForm<0x0D, 1, 0, "stw $RA,$DISP($RB)\t\t!gprellow",
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def STWr : MForm<0x0D, 0, "stw $RA,$DISP($RB)\t\t!gprellow",
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[(truncstorei16 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
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def STL : MForm<0x2C, 1, 0, "stl $RA,$DISP($RB)",
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def STL : MForm<0x2C, 0, "stl $RA,$DISP($RB)",
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[(truncstorei32 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
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def STLr : MForm<0x2C, 1, 0, "stl $RA,$DISP($RB)\t\t!gprellow",
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def STLr : MForm<0x2C, 0, "stl $RA,$DISP($RB)\t\t!gprellow",
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[(truncstorei32 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
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def STQ : MForm<0x2D, 1, 0, "stq $RA,$DISP($RB)",
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def STQ : MForm<0x2D, 0, "stq $RA,$DISP($RB)",
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[(store GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
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def STQr : MForm<0x2D, 1, 0, "stq $RA,$DISP($RB)\t\t!gprellow",
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def STQr : MForm<0x2D, 0, "stq $RA,$DISP($RB)\t\t!gprellow",
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[(store GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
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}
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//Load address
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let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in {
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def LDA : MForm<0x08, 0, 0, "lda $RA,$DISP($RB)",
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def LDA : MForm<0x08, 0, "lda $RA,$DISP($RB)",
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[(set GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_lda>;
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def LDAr : MForm<0x08, 0, 0, "lda $RA,$DISP($RB)\t\t!gprellow",
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def LDAr : MForm<0x08, 0, "lda $RA,$DISP($RB)\t\t!gprellow",
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[(set GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_lda>; //Load address
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def LDAH : MForm<0x09, 0, 0, "ldah $RA,$DISP($RB)",
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def LDAH : MForm<0x09, 0, "ldah $RA,$DISP($RB)",
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[], s_lda>; //Load address high
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def LDAHr : MForm<0x09, 0, 0, "ldah $RA,$DISP($RB)\t\t!gprelhigh",
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def LDAHr : MForm<0x09, 0, "ldah $RA,$DISP($RB)\t\t!gprelhigh",
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[(set GPRC:$RA, (Alpha_gprelhi tglobaladdr:$DISP, GPRC:$RB))], s_lda>; //Load address high
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}
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let OutOperandList = (ops), InOperandList = (ops F4RC:$RA, s64imm:$DISP, GPRC:$RB) in {
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def STS : MForm<0x26, 1, 0, "sts $RA,$DISP($RB)",
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def STS : MForm<0x26, 0, "sts $RA,$DISP($RB)",
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[(store F4RC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_fst>;
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def STSr : MForm<0x26, 1, 0, "sts $RA,$DISP($RB)\t\t!gprellow",
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def STSr : MForm<0x26, 0, "sts $RA,$DISP($RB)\t\t!gprellow",
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[(store F4RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_fst>;
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}
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let OutOperandList = (ops F4RC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in {
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def LDS : MForm<0x22, 0, 1, "lds $RA,$DISP($RB)",
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def LDS : MForm<0x22, 1, "lds $RA,$DISP($RB)",
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[(set F4RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_fld>;
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def LDSr : MForm<0x22, 0, 1, "lds $RA,$DISP($RB)\t\t!gprellow",
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def LDSr : MForm<0x22, 1, "lds $RA,$DISP($RB)\t\t!gprellow",
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[(set F4RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_fld>;
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}
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let OutOperandList = (ops), InOperandList = (ops F8RC:$RA, s64imm:$DISP, GPRC:$RB) in {
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def STT : MForm<0x27, 1, 0, "stt $RA,$DISP($RB)",
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def STT : MForm<0x27, 0, "stt $RA,$DISP($RB)",
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[(store F8RC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_fst>;
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def STTr : MForm<0x27, 1, 0, "stt $RA,$DISP($RB)\t\t!gprellow",
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def STTr : MForm<0x27, 0, "stt $RA,$DISP($RB)\t\t!gprellow",
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[(store F8RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_fst>;
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}
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let OutOperandList = (ops F8RC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in {
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def LDT : MForm<0x23, 0, 1, "ldt $RA,$DISP($RB)",
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def LDT : MForm<0x23, 1, "ldt $RA,$DISP($RB)",
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[(set F8RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_fld>;
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def LDTr : MForm<0x23, 0, 1, "ldt $RA,$DISP($RB)\t\t!gprellow",
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def LDTr : MForm<0x23, 1, "ldt $RA,$DISP($RB)\t\t!gprellow",
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[(set F8RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_fld>;
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}
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@ -557,13 +557,13 @@ def : Pat<(truncstorei8 GPRC:$DATA, GPRC:$addr),
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//load address, rellocated gpdist form
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let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s16imm:$DISP, GPRC:$RB, s16imm:$NUM) in {
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def LDAg : MForm<0x08, 0, 1, "lda $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>; //Load address
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def LDAHg : MForm<0x09, 0, 1, "ldah $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>; //Load address
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def LDAg : MForm<0x08, 1, "lda $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>; //Load address
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def LDAHg : MForm<0x09, 1, "ldah $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>; //Load address
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}
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//Load quad, rellocated literal form
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let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in
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def LDQl : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!literal",
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def LDQl : MForm<0x29, 1, "ldq $RA,$DISP($RB)\t\t!literal",
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[(set GPRC:$RA, (Alpha_rellit tglobaladdr:$DISP, GPRC:$RB))], s_ild>;
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def : Pat<(Alpha_rellit texternalsym:$ext, GPRC:$RB),
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(LDQl texternalsym:$ext, GPRC:$RB)>;
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@ -257,179 +257,177 @@ let isLoad = 1 in {
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// Stores:
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//===----------------------------------------------------------------------===//
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let isStore = 1 in {
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def STQDv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store (v16i8 VECREG:$rT), dform_addr:$src)]>;
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def STQDv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store (v16i8 VECREG:$rT), dform_addr:$src)]>;
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def STQDv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store (v8i16 VECREG:$rT), dform_addr:$src)]>;
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def STQDv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store (v8i16 VECREG:$rT), dform_addr:$src)]>;
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def STQDv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store (v4i32 VECREG:$rT), dform_addr:$src)]>;
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def STQDv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store (v4i32 VECREG:$rT), dform_addr:$src)]>;
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def STQDv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store (v2i64 VECREG:$rT), dform_addr:$src)]>;
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def STQDv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store (v2i64 VECREG:$rT), dform_addr:$src)]>;
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def STQDv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store (v4f32 VECREG:$rT), dform_addr:$src)]>;
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def STQDv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store (v4f32 VECREG:$rT), dform_addr:$src)]>;
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def STQDv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store (v2f64 VECREG:$rT), dform_addr:$src)]>;
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def STQDv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store (v2f64 VECREG:$rT), dform_addr:$src)]>;
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def STQDr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store GPRC:$rT, dform_addr:$src)]>;
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def STQDr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store GPRC:$rT, dform_addr:$src)]>;
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def STQDr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store R64C:$rT, dform_addr:$src)]>;
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def STQDr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store R64C:$rT, dform_addr:$src)]>;
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def STQDr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store R32C:$rT, dform_addr:$src)]>;
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def STQDr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store R32C:$rT, dform_addr:$src)]>;
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// Floating Point
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def STQDf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store R32FP:$rT, dform_addr:$src)]>;
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// Floating Point
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def STQDf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store R32FP:$rT, dform_addr:$src)]>;
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def STQDf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store R64FP:$rT, dform_addr:$src)]>;
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def STQDf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store R64FP:$rT, dform_addr:$src)]>;
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def STQDr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store R16C:$rT, dform_addr:$src)]>;
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def STQDr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store R16C:$rT, dform_addr:$src)]>;
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def STQDr8 : RI10Form<0b00100100, (outs), (ins R8C:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store R8C:$rT, dform_addr:$src)]>;
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def STQDr8 : RI10Form<0b00100100, (outs), (ins R8C:$rT, memri10:$src),
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"stqd\t$rT, $src", LoadStore,
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[(store R8C:$rT, dform_addr:$src)]>;
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def STQAv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
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"stqa\t$rT, $src", LoadStore,
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[(store (v16i8 VECREG:$rT), aform_addr:$src)]>;
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def STQAv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
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"stqa\t$rT, $src", LoadStore,
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[(store (v16i8 VECREG:$rT), aform_addr:$src)]>;
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def STQAv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
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"stqa\t$rT, $src", LoadStore,
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[(store (v8i16 VECREG:$rT), aform_addr:$src)]>;
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def STQAv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
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"stqa\t$rT, $src", LoadStore,
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[(store (v8i16 VECREG:$rT), aform_addr:$src)]>;
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def STQAv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
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"stqa\t$rT, $src", LoadStore,
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[(store (v4i32 VECREG:$rT), aform_addr:$src)]>;
|
||||
def STQAv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
|
||||
"stqa\t$rT, $src", LoadStore,
|
||||
[(store (v4i32 VECREG:$rT), aform_addr:$src)]>;
|
||||
|
||||
def STQAv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
|
||||
"stqa\t$rT, $src", LoadStore,
|
||||
[(store (v2i64 VECREG:$rT), aform_addr:$src)]>;
|
||||
def STQAv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
|
||||
"stqa\t$rT, $src", LoadStore,
|
||||
[(store (v2i64 VECREG:$rT), aform_addr:$src)]>;
|
||||
|
||||
def STQAv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
|
||||
"stqa\t$rT, $src", LoadStore,
|
||||
[(store (v4f32 VECREG:$rT), aform_addr:$src)]>;
|
||||
def STQAv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
|
||||
"stqa\t$rT, $src", LoadStore,
|
||||
[(store (v4f32 VECREG:$rT), aform_addr:$src)]>;
|
||||
|
||||
def STQAv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
|
||||
"stqa\t$rT, $src", LoadStore,
|
||||
[(store (v2f64 VECREG:$rT), aform_addr:$src)]>;
|
||||
def STQAv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
|
||||
"stqa\t$rT, $src", LoadStore,
|
||||
[(store (v2f64 VECREG:$rT), aform_addr:$src)]>;
|
||||
|
||||
def STQAr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, addr256k:$src),
|
||||
"stqa\t$rT, $src", LoadStore,
|
||||
[(store GPRC:$rT, aform_addr:$src)]>;
|
||||
def STQAr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, addr256k:$src),
|
||||
"stqa\t$rT, $src", LoadStore,
|
||||
[(store GPRC:$rT, aform_addr:$src)]>;
|
||||
|
||||
def STQAr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, addr256k:$src),
|
||||
"stqa\t$rT, $src", LoadStore,
|
||||
[(store R64C:$rT, aform_addr:$src)]>;
|
||||
def STQAr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, addr256k:$src),
|
||||
"stqa\t$rT, $src", LoadStore,
|
||||
[(store R64C:$rT, aform_addr:$src)]>;
|
||||
|
||||
def STQAr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, addr256k:$src),
|
||||
"stqa\t$rT, $src", LoadStore,
|
||||
[(store R32C:$rT, aform_addr:$src)]>;
|
||||
def STQAr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, addr256k:$src),
|
||||
"stqa\t$rT, $src", LoadStore,
|
||||
[(store R32C:$rT, aform_addr:$src)]>;
|
||||
|
||||
// Floating Point
|
||||
def STQAf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, addr256k:$src),
|
||||
"stqa\t$rT, $src", LoadStore,
|
||||
[(store R32FP:$rT, aform_addr:$src)]>;
|
||||
// Floating Point
|
||||
def STQAf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, addr256k:$src),
|
||||
"stqa\t$rT, $src", LoadStore,
|
||||
[(store R32FP:$rT, aform_addr:$src)]>;
|
||||
|
||||
def STQAf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, addr256k:$src),
|
||||
"stqa\t$rT, $src", LoadStore,
|
||||
[(store R64FP:$rT, aform_addr:$src)]>;
|
||||
def STQAf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, addr256k:$src),
|
||||
"stqa\t$rT, $src", LoadStore,
|
||||
[(store R64FP:$rT, aform_addr:$src)]>;
|
||||
|
||||
def STQAr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, addr256k:$src),
|
||||
"stqa\t$rT, $src", LoadStore,
|
||||
[(store R16C:$rT, aform_addr:$src)]>;
|
||||
|
||||
def STQAr8 : RI10Form<0b00100100, (outs), (ins R8C:$rT, addr256k:$src),
|
||||
"stqa\t$rT, $src", LoadStore,
|
||||
[(store R8C:$rT, aform_addr:$src)]>;
|
||||
def STQAr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, addr256k:$src),
|
||||
"stqa\t$rT, $src", LoadStore,
|
||||
[(store R16C:$rT, aform_addr:$src)]>;
|
||||
|
||||
def STQXv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store (v16i8 VECREG:$rT), xform_addr:$src)]>;
|
||||
def STQAr8 : RI10Form<0b00100100, (outs), (ins R8C:$rT, addr256k:$src),
|
||||
"stqa\t$rT, $src", LoadStore,
|
||||
[(store R8C:$rT, aform_addr:$src)]>;
|
||||
|
||||
def STQXv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store (v8i16 VECREG:$rT), xform_addr:$src)]>;
|
||||
def STQXv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store (v16i8 VECREG:$rT), xform_addr:$src)]>;
|
||||
|
||||
def STQXv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store (v4i32 VECREG:$rT), xform_addr:$src)]>;
|
||||
def STQXv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store (v8i16 VECREG:$rT), xform_addr:$src)]>;
|
||||
|
||||
def STQXv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store (v2i64 VECREG:$rT), xform_addr:$src)]>;
|
||||
def STQXv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store (v4i32 VECREG:$rT), xform_addr:$src)]>;
|
||||
|
||||
def STQXv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store (v4f32 VECREG:$rT), xform_addr:$src)]>;
|
||||
def STQXv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store (v2i64 VECREG:$rT), xform_addr:$src)]>;
|
||||
|
||||
def STQXv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store (v2f64 VECREG:$rT), xform_addr:$src)]>;
|
||||
def STQXv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store (v4f32 VECREG:$rT), xform_addr:$src)]>;
|
||||
|
||||
def STQXr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store GPRC:$rT, xform_addr:$src)]>;
|
||||
def STQXv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store (v2f64 VECREG:$rT), xform_addr:$src)]>;
|
||||
|
||||
def STQXr64:
|
||||
RI10Form<0b00100100, (outs), (ins R64C:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store R64C:$rT, xform_addr:$src)]>;
|
||||
def STQXr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store GPRC:$rT, xform_addr:$src)]>;
|
||||
|
||||
def STQXr32:
|
||||
RI10Form<0b00100100, (outs), (ins R32C:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store R32C:$rT, xform_addr:$src)]>;
|
||||
def STQXr64:
|
||||
RI10Form<0b00100100, (outs), (ins R64C:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store R64C:$rT, xform_addr:$src)]>;
|
||||
|
||||
// Floating Point
|
||||
def STQXf32:
|
||||
RI10Form<0b00100100, (outs), (ins R32FP:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store R32FP:$rT, xform_addr:$src)]>;
|
||||
def STQXr32:
|
||||
RI10Form<0b00100100, (outs), (ins R32C:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store R32C:$rT, xform_addr:$src)]>;
|
||||
|
||||
def STQXf64:
|
||||
RI10Form<0b00100100, (outs), (ins R64FP:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store R64FP:$rT, xform_addr:$src)]>;
|
||||
// Floating Point
|
||||
def STQXf32:
|
||||
RI10Form<0b00100100, (outs), (ins R32FP:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store R32FP:$rT, xform_addr:$src)]>;
|
||||
|
||||
def STQXr16:
|
||||
RI10Form<0b00100100, (outs), (ins R16C:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store R16C:$rT, xform_addr:$src)]>;
|
||||
|
||||
def STQXr8:
|
||||
RI10Form<0b00100100, (outs), (ins R8C:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store R8C:$rT, xform_addr:$src)]>;
|
||||
def STQXf64:
|
||||
RI10Form<0b00100100, (outs), (ins R64FP:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store R64FP:$rT, xform_addr:$src)]>;
|
||||
|
||||
def STQXr16:
|
||||
RI10Form<0b00100100, (outs), (ins R16C:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store R16C:$rT, xform_addr:$src)]>;
|
||||
|
||||
def STQXr8:
|
||||
RI10Form<0b00100100, (outs), (ins R8C:$rT, memrr:$src),
|
||||
"stqx\t$rT, $src", LoadStore,
|
||||
[(store R8C:$rT, xform_addr:$src)]>;
|
||||
|
||||
/* Store quadword, PC relative: Not much use at this point in time. Might
|
||||
be useful for relocatable code.
|
||||
def STQR : RI16Form<0b111000100, (outs), (ins VECREG:$rT, s16imm:$disp),
|
||||
"stqr\t$rT, $disp", LoadStore,
|
||||
[(store VECREG:$rT, iaddr:$disp)]>;
|
||||
*/
|
||||
}
|
||||
be useful for relocatable code.
|
||||
def STQR : RI16Form<0b111000100, (outs), (ins VECREG:$rT, s16imm:$disp),
|
||||
"stqr\t$rT, $disp", LoadStore,
|
||||
[(store VECREG:$rT, iaddr:$disp)]>;
|
||||
*/
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Generate Controls for Insertion:
|
||||
|
|
|
|||
|
|
@ -213,7 +213,6 @@ class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
|
|||
!strconcat(instr_asm, " $dst, $addr"),
|
||||
[(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
|
||||
|
||||
let isStore = 1 in
|
||||
class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
|
||||
FI< op,
|
||||
(outs),
|
||||
|
|
|
|||
|
|
@ -513,14 +513,10 @@ def STDU : DSForm_1<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
|
|||
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
|
||||
isPPC64;
|
||||
|
||||
}
|
||||
|
||||
let isStore = 1, PPC970_Unit = 2 in {
|
||||
|
||||
let isStore = 1 in
|
||||
def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst),
|
||||
"stdux $rS, $dst", LdStSTD,
|
||||
[]>, isPPC64;
|
||||
|
||||
|
||||
// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
|
||||
def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst),
|
||||
|
|
|
|||
|
|
@ -52,7 +52,8 @@ def SDT_PPCstbrx : SDTypeProfile<0, 4, [
|
|||
def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
|
||||
def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
|
||||
def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
|
||||
def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>;
|
||||
def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
|
||||
[SDNPHasChain, SDNPMayStore]>;
|
||||
|
||||
// This sequence is used for long double->int conversions. It changes the
|
||||
// bits in the FPSCR which is not modelled.
|
||||
|
|
@ -88,7 +89,8 @@ def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
|
|||
def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
|
||||
|
||||
def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
|
||||
def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>;
|
||||
def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
|
||||
[SDNPHasChain, SDNPMayStore]>;
|
||||
|
||||
// These are target-independent nodes, but have target-specific formats.
|
||||
def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
|
||||
|
|
@ -119,7 +121,8 @@ def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
|
|||
[SDNPHasChain, SDNPOptInFlag]>;
|
||||
|
||||
def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain]>;
|
||||
def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, [SDNPHasChain]>;
|
||||
def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
|
||||
[SDNPHasChain, SDNPMayStore]>;
|
||||
|
||||
// Instructions to support dynamic alloca.
|
||||
def SDTDynOp : SDTypeProfile<1, 2, []>;
|
||||
|
|
@ -639,6 +642,7 @@ let isStore = 1 in {
|
|||
def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
"stwux $rS, $rA, $rB", LdStGeneral,
|
||||
[]>;
|
||||
}
|
||||
def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
|
||||
"sthbrx $rS, $dst", LdStGeneral,
|
||||
[(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>,
|
||||
|
|
@ -651,7 +655,7 @@ def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
|
|||
def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
|
||||
"stfiwx $frS, $dst", LdStUX,
|
||||
[(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
|
||||
}
|
||||
|
||||
def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
|
||||
"stfsx $frS, $dst", LdStUX,
|
||||
[(store F4RC:$frS, xaddr:$dst)]>;
|
||||
|
|
|
|||
|
|
@ -189,6 +189,7 @@ def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
|
|||
def SDNPOutFlag : SDNodeProperty; // Write a flag result
|
||||
def SDNPInFlag : SDNodeProperty; // Read a flag operand
|
||||
def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
|
||||
def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'isStore'.
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Selection DAG Node definitions.
|
||||
|
|
@ -313,8 +314,10 @@ def ret : SDNode<"ISD::RET" , SDTRet, [SDNPHasChain]>;
|
|||
// Do not use ld, st directly. Use load, extload, sextload, zextload, store,
|
||||
// and truncst (see below).
|
||||
def ld : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>;
|
||||
def st : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>;
|
||||
def ist : SDNode<"ISD::STORE" , SDTIStore, [SDNPHasChain]>;
|
||||
def st : SDNode<"ISD::STORE" , SDTStore,
|
||||
[SDNPHasChain, SDNPMayStore]>;
|
||||
def ist : SDNode<"ISD::STORE" , SDTIStore,
|
||||
[SDNPHasChain, SDNPMayStore]>;
|
||||
|
||||
def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
|
||||
def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>;
|
||||
|
|
|
|||
|
|
@ -317,6 +317,8 @@ SDNodeInfo::SDNodeInfo(Record *R) : Def(R) {
|
|||
Properties |= 1 << SDNPInFlag;
|
||||
} else if (PropList[i]->getName() == "SDNPOptInFlag") {
|
||||
Properties |= 1 << SDNPOptInFlag;
|
||||
} else if (PropList[i]->getName() == "SDNPMayStore") {
|
||||
Properties |= 1 << SDNPMayStore;
|
||||
} else {
|
||||
cerr << "Unknown SD Node property '" << PropList[i]->getName()
|
||||
<< "' on node '" << R->getName() << "'!\n";
|
||||
|
|
|
|||
|
|
@ -30,8 +30,15 @@ struct CodeGenRegister;
|
|||
class CodeGenTarget;
|
||||
|
||||
// SelectionDAG node properties.
|
||||
enum SDNP { SDNPCommutative, SDNPAssociative, SDNPHasChain,
|
||||
SDNPOutFlag, SDNPInFlag, SDNPOptInFlag };
|
||||
enum SDNP {
|
||||
SDNPCommutative,
|
||||
SDNPAssociative,
|
||||
SDNPHasChain,
|
||||
SDNPOutFlag,
|
||||
SDNPInFlag,
|
||||
SDNPOptInFlag,
|
||||
SDNPMayStore
|
||||
};
|
||||
|
||||
/// getValueType - Return the MVT::ValueType that the specified TableGen record
|
||||
/// corresponds to.
|
||||
|
|
|
|||
|
|
@ -157,9 +157,7 @@ public:
|
|||
if (Pattern == 0) return; // No pattern.
|
||||
|
||||
// Assume there is no side-effect unless we see one.
|
||||
// FIXME: Enable this.
|
||||
//NeverHasSideEffects = true;
|
||||
|
||||
NeverHasSideEffects = true;
|
||||
|
||||
// FIXME: Assume only the first tree is the pattern. The others are clobber
|
||||
// nodes.
|
||||
|
|
@ -176,10 +174,9 @@ private:
|
|||
// Get information about the SDNode for the operator.
|
||||
const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N->getOperator());
|
||||
|
||||
// If this is a store node, it obviously stores to memory.
|
||||
if (OpInfo.getEnumName() == "ISD::STORE") {
|
||||
// If node writes to memory, it obviously stores to memory.
|
||||
if (OpInfo.hasProperty(SDNPMayStore)) {
|
||||
isStore = true;
|
||||
|
||||
} else if (const CodeGenIntrinsic *IntInfo = N->getIntrinsicInfo(CDP)) {
|
||||
// If this is an intrinsic, analyze it.
|
||||
if (IntInfo->ModRef >= CodeGenIntrinsic::WriteArgMem)
|
||||
|
|
@ -196,15 +193,30 @@ private:
|
|||
void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst,
|
||||
bool &isStore, bool &isLoad,
|
||||
bool &NeverHasSideEffects) {
|
||||
isStore = Inst.isStore;
|
||||
isLoad = Inst.isLoad;
|
||||
NeverHasSideEffects = Inst.neverHasSideEffects;
|
||||
isStore = isLoad = NeverHasSideEffects = false;
|
||||
|
||||
InstAnalyzer(CDP, isStore, isLoad, NeverHasSideEffects).Analyze(Inst.TheDef);
|
||||
|
||||
|
||||
// InstAnalyzer only correctly analyzes isStore so far.
|
||||
if (Inst.isStore) { // If the .td file explicitly sets isStore, use it.
|
||||
// If we decided that this is a store from the pattern, then the .td file
|
||||
// entry is redundant.
|
||||
if (isStore)
|
||||
fprintf(stderr, "Warning: isStore flag explicitly set on instruction '%s'"
|
||||
" but flag already inferred from pattern.\n",
|
||||
Inst.getName().c_str());
|
||||
isStore = true;
|
||||
}
|
||||
|
||||
// These two override everything.
|
||||
isLoad = Inst.isLoad;
|
||||
NeverHasSideEffects = Inst.neverHasSideEffects;
|
||||
|
||||
#if 0
|
||||
// If the .td file explicitly says there is no side effect, believe it.
|
||||
if (Inst.neverHasSideEffects)
|
||||
NeverHasSideEffects = true;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue