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Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding 

bits.  Johnny, please review -- I do not have a good track record of getting
these right.

llvm-svn: 85173
This commit is contained in:
Bob Wilson 2009-10-26 22:59:12 +00:00
parent e45ac76ee4
commit a33fa47141
1 changed files with 16 additions and 2 deletions
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18
llvm/lib/Target/ARM/ARMInstrInfo.td
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@ -1092,6 +1092,7 @@ defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm, def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
IIC_iALUi, "rsb", " $dst, $a, $b", IIC_iALUi, "rsb", " $dst, $a, $b",
[(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> { [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
let Inst{20} = 0;
let Inst{25} = 1; let Inst{25} = 1;
} }
@ -1100,6 +1101,7 @@ def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
[(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> { [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {
let Inst{4} = 1; let Inst{4} = 1;
let Inst{7} = 0; let Inst{7} = 0;
let Inst{20} = 0;
let Inst{25} = 0; let Inst{25} = 0;
} }
@ -1126,12 +1128,18 @@ def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
DPFrm, IIC_iALUi, "rsc", " $dst, $a, $b", DPFrm, IIC_iALUi, "rsc", " $dst, $a, $b",
[(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>, [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
Requires<[IsARM, CarryDefIsUnused]> { Requires<[IsARM, CarryDefIsUnused]> {
let Inst{20} = 0;
let Inst{25} = 1; let Inst{25} = 1;
} }
def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
DPSoRegFrm, IIC_iALUsr, "rsc", " $dst, $a, $b", DPSoRegFrm, IIC_iALUsr, "rsc", " $dst, $a, $b",
[(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>, [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
Requires<[IsARM, CarryDefIsUnused]>; Requires<[IsARM, CarryDefIsUnused]> {
let Inst{4} = 1;
let Inst{7} = 0;
let Inst{20} = 0;
let Inst{25} = 0;
}
} }
// FIXME: Allow these to be predicated. // FIXME: Allow these to be predicated.
@ -1140,12 +1148,18 @@ def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
DPFrm, IIC_iALUi, "rscs $dst, $a, $b", DPFrm, IIC_iALUi, "rscs $dst, $a, $b",
[(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>, [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
Requires<[IsARM, CarryDefIsUnused]> { Requires<[IsARM, CarryDefIsUnused]> {
let Inst{20} = 1;
let Inst{25} = 1; let Inst{25} = 1;
} }
def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
DPSoRegFrm, IIC_iALUsr, "rscs $dst, $a, $b", DPSoRegFrm, IIC_iALUsr, "rscs $dst, $a, $b",
[(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>, [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
Requires<[IsARM, CarryDefIsUnused]>; Requires<[IsARM, CarryDefIsUnused]> {
let Inst{4} = 1;
let Inst{7} = 0;
let Inst{20} = 1;
let Inst{25} = 0;
}
} }
// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.