forked from OSchip/llvm-project
Continue Alkis's int64_t cleanup. This makes all of the immediate related
methods take an int or unsigned value instead of int64_t. Also, add an 'addImm' method to the MachineInstrBuilder class, because the fact that the hardware sign or zero extends it does not/should not matter to the code generator. Once the old sparc backend is removed the difference can be eliminated. llvm-svn: 11976
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@ -128,7 +128,7 @@ private:
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int regNum; // register number for an explicit register
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int regNum; // register number for an explicit register
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// will be set for a value after reg allocation
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// will be set for a value after reg allocation
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private:
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private:
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MachineOperand(int64_t ImmVal = 0, MachineOperandType OpTy = MO_VirtualRegister)
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MachineOperand(int ImmVal = 0, MachineOperandType OpTy = MO_VirtualRegister)
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: immedVal(ImmVal),
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: immedVal(ImmVal),
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flags(0),
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flags(0),
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opType(OpTy),
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opType(OpTy),
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@ -228,8 +228,8 @@ public:
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assert(opType == MO_MachineRegister);
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assert(opType == MO_MachineRegister);
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return regNum;
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return regNum;
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}
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}
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int64_t getImmedValue() const { assert(isImmediate()); return immedVal; }
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int getImmedValue() const { assert(isImmediate()); return immedVal; }
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void setImmedValue(int64_t ImmVal) { assert(isImmediate()); immedVal=ImmVal; }
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void setImmedValue(int ImmVal) { assert(isImmediate()); immedVal = ImmVal; }
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MachineBasicBlock *getMachineBasicBlock() const {
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MachineBasicBlock *getMachineBasicBlock() const {
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assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!");
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assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!");
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@ -522,7 +522,7 @@ public:
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/// addZeroExtImmOperand - Add a zero extended constant argument to the
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/// addZeroExtImmOperand - Add a zero extended constant argument to the
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/// machine instruction.
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/// machine instruction.
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///
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///
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void addZeroExtImmOperand(int64_t intValue) {
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void addZeroExtImmOperand(int intValue) {
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assert(!OperandsComplete() &&
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assert(!OperandsComplete() &&
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"Trying to add an operand to a machine instr that is already done!");
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"Trying to add an operand to a machine instr that is already done!");
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operands.push_back(
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operands.push_back(
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@ -532,7 +532,7 @@ public:
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/// addSignExtImmOperand - Add a zero extended constant argument to the
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/// addSignExtImmOperand - Add a zero extended constant argument to the
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/// machine instruction.
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/// machine instruction.
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///
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///
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void addSignExtImmOperand(int64_t intValue) {
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void addSignExtImmOperand(int intValue) {
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assert(!OperandsComplete() &&
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assert(!OperandsComplete() &&
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"Trying to add an operand to a machine instr that is already done!");
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"Trying to add an operand to a machine instr that is already done!");
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operands.push_back(
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operands.push_back(
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@ -600,13 +600,13 @@ public:
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// Access to set the operands when building the machine instruction
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// Access to set the operands when building the machine instruction
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//
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//
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void SetMachineOperandVal (unsigned i,
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void SetMachineOperandVal(unsigned i,
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MachineOperand::MachineOperandType operandType,
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MachineOperand::MachineOperandType operandType,
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Value* V);
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Value* V);
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void SetMachineOperandConst (unsigned i,
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void SetMachineOperandConst(unsigned i,
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MachineOperand::MachineOperandType operandType,
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MachineOperand::MachineOperandType operandType,
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int64_t intValue);
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int intValue);
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void SetMachineOperandReg(unsigned i, int regNum);
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void SetMachineOperandReg(unsigned i, int regNum);
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@ -80,23 +80,29 @@ public:
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/// addMReg - Add a machine register operand...
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/// addMReg - Add a machine register operand...
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///
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///
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const MachineInstrBuilder &addMReg(
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const MachineInstrBuilder &addMReg(int Reg, MachineOperand::UseType Ty
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int Reg,
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= MachineOperand::Use) const {
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MachineOperand::UseType Ty = MachineOperand::Use) const {
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MI->addMachineRegOperand(Reg, Ty);
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MI->addMachineRegOperand(Reg, Ty);
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return *this;
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return *this;
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}
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}
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/// addImm - Add a new immediate operand.
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///
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const MachineInstrBuilder &addImm(int Val) const {
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MI->addZeroExtImmOperand(Val);
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return *this;
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}
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/// addSImm - Add a new sign extended immediate operand...
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/// addSImm - Add a new sign extended immediate operand...
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///
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///
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const MachineInstrBuilder &addSImm(int64_t val) const {
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const MachineInstrBuilder &addSImm(int val) const {
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MI->addSignExtImmOperand(val);
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MI->addSignExtImmOperand(val);
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return *this;
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return *this;
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}
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}
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/// addZImm - Add a new zero extended immediate operand...
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/// addZImm - Add a new zero extended immediate operand...
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///
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///
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const MachineInstrBuilder &addZImm(int64_t Val) const {
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const MachineInstrBuilder &addZImm(unsigned Val) const {
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MI->addZeroExtImmOperand(Val);
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MI->addZeroExtImmOperand(Val);
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return *this;
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return *this;
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}
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}
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