forked from OSchip/llvm-project
[mips] Include EVA instructions in Std2MicroMips mapping tables
This patch includes EVA instructions in the Std2MicroMips mapping tables, which is required for direct object emission. Differential Revision: https://reviews.llvm.org/D41771 llvm-svn: 323958
This commit is contained in:
Aleksandar Beserminji
parent
cda2526d86
commit
a330c208f2
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@ -699,7 +699,7 @@ class LL_FM_MM<bits<4> funct> : MMArch {
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let Inst{11-0} = addr{11-0};
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}
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class LLE_FM_MM<bits<4> funct> {
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class LLE_FM_MM<bits<4> funct> : MMArch {
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bits<5> rt;
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bits<21> addr;
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bits<5> base = addr{20-16};
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@ -273,6 +273,7 @@ class LLEBaseMM<string opstr, RegisterOperand RO> :
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InstSE<(outs RO:$rt), (ins mem_simm9:$addr),
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!strconcat(opstr, "\t$rt, $addr"), [], II_LLE, FrmI> {
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let DecoderMethod = "DecodeMemMMImm9";
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string BaseOpcode = opstr;
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let mayLoad = 1;
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}
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@ -288,6 +289,7 @@ class SCEBaseMM<string opstr, RegisterOperand RO> :
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InstSE<(outs RO:$dst), (ins RO:$rt, mem_simm9:$addr),
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!strconcat(opstr, "\t$rt, $addr"), [], II_SCE, FrmI> {
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let DecoderMethod = "DecodeMemMMImm9";
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string BaseOpcode = opstr;
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let mayStore = 1;
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let Constraints = "$rt = $dst";
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}
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@ -777,21 +779,27 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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}
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let DecoderMethod = "DecodeMemMMImm9" in {
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def LBE_MM : Load<"lbe", GPR32Opnd, null_frag, II_LBE>,
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def LBE_MM : MMRel, Load<"lbe", GPR32Opnd, null_frag, II_LBE>,
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POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>;
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def LBuE_MM : Load<"lbue", GPR32Opnd, null_frag, II_LBUE>,
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def LBuE_MM : MMRel, Load<"lbue", GPR32Opnd, null_frag, II_LBUE>,
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POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>;
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def LHE_MM : LoadMemory<"lhe", GPR32Opnd, mem_simm9, null_frag, II_LHE>,
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def LHE_MM : MMRel, LoadMemory<"lhe", GPR32Opnd, mem_simm9,
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null_frag, II_LHE>,
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POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>;
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def LHuE_MM : LoadMemory<"lhue", GPR32Opnd, mem_simm9, null_frag, II_LHUE>,
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def LHuE_MM : MMRel, LoadMemory<"lhue", GPR32Opnd, mem_simm9,
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null_frag, II_LHUE>,
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POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>;
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def LWE_MM : LoadMemory<"lwe", GPR32Opnd, mem_simm9, null_frag, II_LWE>,
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def LWE_MM : MMRel, LoadMemory<"lwe", GPR32Opnd, mem_simm9,
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null_frag, II_LWE>,
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POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>;
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def SBE_MM : StoreMemory<"sbe", GPR32Opnd, mem_simm9, null_frag, II_SBE>,
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def SBE_MM : MMRel, StoreMemory<"sbe", GPR32Opnd, mem_simm9,
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null_frag, II_SBE>,
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POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>;
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def SHE_MM : StoreMemory<"she", GPR32Opnd, mem_simm9, null_frag, II_SHE>,
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def SHE_MM : MMRel, StoreMemory<"she", GPR32Opnd, mem_simm9,
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null_frag, II_SHE>,
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POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>;
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def SWE_MM : StoreMemory<"swe", GPR32Opnd, mem_simm9, null_frag, II_SWE>,
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def SWE_MM : MMRel, StoreMemory<"swe", GPR32Opnd, mem_simm9,
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null_frag, II_SWE>,
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POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>;
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}
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@ -971,8 +979,8 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
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def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
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def LLE_MM : LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>;
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def SCE_MM : SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>;
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def LLE_MM : MMRel, LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>;
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def SCE_MM : MMRel, SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>;
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let DecoderMethod = "DecodeCacheOpMM" in {
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def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12, II_CACHE>,
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@ -59,6 +59,7 @@ class LOAD_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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list<dag> Pattern = [];
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string DecoderMethod = "DecodeMemEVA";
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bit canFoldAsLoad = 1;
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string BaseOpcode = instr_asm;
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bit mayLoad = 1;
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InstrItinClass Itinerary = itin;
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}
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@ -77,6 +78,7 @@ class STORE_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
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list<dag> Pattern = [];
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string DecoderMethod = "DecodeMemEVA";
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string BaseOpcode = instr_asm;
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bit mayStore = 1;
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InstrItinClass Itinerary = itin;
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}
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@ -121,6 +123,7 @@ class LLE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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dag InOperandList = (ins mem_simm9:$addr);
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string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
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list<dag> Pattern = [];
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string BaseOpcode = instr_asm;
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bit mayLoad = 1;
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string DecoderMethod = "DecodeMemEVA";
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InstrItinClass Itinerary = itin;
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@ -134,6 +137,7 @@ class SCE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
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string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
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list<dag> Pattern = [];
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string BaseOpcode = instr_asm;
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bit mayStore = 1;
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string Constraints = "$rt = $dst";
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string DecoderMethod = "DecodeMemEVA";
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@ -159,6 +163,7 @@ class CACHEE_DESC_BASE<string instr_asm, Operand MemOpnd,
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dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
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string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
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list<dag> Pattern = [];
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string BaseOpcode = instr_asm;
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string DecoderMethod = "DecodeCacheeOp_CacheOpR6";
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InstrItinClass Itinerary = itin;
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}
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@ -173,17 +178,17 @@ class PREFE_DESC : CACHEE_DESC_BASE<"prefe", mem_simm9, II_PREFE>;
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//===----------------------------------------------------------------------===//
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/// Load and Store EVA Instructions
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def LBE : LBE_ENC, LBE_DESC, INSN_EVA;
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def LBuE : LBuE_ENC, LBuE_DESC, INSN_EVA;
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def LHE : LHE_ENC, LHE_DESC, INSN_EVA;
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def LHuE : LHuE_ENC, LHuE_DESC, INSN_EVA;
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def LBE : MMRel, LBE_ENC, LBE_DESC, INSN_EVA;
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def LBuE : MMRel, LBuE_ENC, LBuE_DESC, INSN_EVA;
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def LHE : MMRel, LHE_ENC, LHE_DESC, INSN_EVA;
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def LHuE : MMRel, LHuE_ENC, LHuE_DESC, INSN_EVA;
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let AdditionalPredicates = [NotInMicroMips] in {
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def LWE : LWE_ENC, LWE_DESC, INSN_EVA;
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def LWE : MMRel, LWE_ENC, LWE_DESC, INSN_EVA;
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}
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def SBE : SBE_ENC, SBE_DESC, INSN_EVA;
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def SHE : SHE_ENC, SHE_DESC, INSN_EVA;
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def SBE : MMRel, SBE_ENC, SBE_DESC, INSN_EVA;
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def SHE : MMRel, SHE_ENC, SHE_DESC, INSN_EVA;
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let AdditionalPredicates = [NotInMicroMips] in {
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def SWE : SWE_ENC, SWE_DESC, INSN_EVA;
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def SWE : MMRel, SWE_ENC, SWE_DESC, INSN_EVA;
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}
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/// load/store left/right EVA
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@ -196,8 +201,8 @@ def SWRE : SWRE_ENC, SWRE_DESC, INSN_EVA_NOT_32R6_64R6;
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/// Load-linked EVA, Store-conditional EVA
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let AdditionalPredicates = [NotInMicroMips] in {
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def LLE : LLE_ENC, LLE_DESC, INSN_EVA;
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def SCE : SCE_ENC, SCE_DESC, INSN_EVA;
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def LLE : MMRel, LLE_ENC, LLE_DESC, INSN_EVA;
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def SCE : MMRel, SCE_ENC, SCE_DESC, INSN_EVA;
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}
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let AdditionalPredicates = [NotInMicroMips] in {
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@ -205,5 +210,5 @@ let AdditionalPredicates = [NotInMicroMips] in {
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def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, INSN_EVA;
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}
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def CACHEE : CACHEE_ENC, CACHEE_DESC, INSN_EVA;
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def PREFE : PREFE_ENC, PREFE_DESC, INSN_EVA;
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def CACHEE : MMRel, CACHEE_ENC, CACHEE_DESC, INSN_EVA;
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def PREFE : MMRel, PREFE_ENC, PREFE_DESC, INSN_EVA;
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@ -1333,6 +1333,7 @@ class LoadMemory<string opstr, DAGOperand RO, DAGOperand MO,
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[(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
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let DecoderMethod = "DecodeMem";
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let canFoldAsLoad = 1;
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string BaseOpcode = opstr;
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let mayLoad = 1;
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}
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@ -1346,6 +1347,7 @@ class StoreMemory<string opstr, DAGOperand RO, DAGOperand MO,
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InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
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[(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
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let DecoderMethod = "DecodeMem";
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string BaseOpcode = opstr;
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let mayStore = 1;
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}
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@ -0,0 +1,213 @@
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# RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips -start-after=expand-isel-pseudos \
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# RUN: -filetype obj %s -o - | llvm-objdump -d - | FileCheck %s
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--- |
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@wArray = global [13 x i32] zeroinitializer, align 4
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@hArray = global [13 x i16] zeroinitializer, align 2
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@bArray = global [13 x i8] zeroinitializer, align 1
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; Function Attrs: noinline nounwind optnone
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define void @_Z3foov() {
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entry:
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%0 = load i8, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @bArray, i32 0, i32 5), align 1
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%conv = sext i8 %0 to i32
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%sub = sub nsw i32 %conv, 7
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%conv1 = trunc i32 %sub to i8
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store i8 %conv1, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @bArray, i32 0, i32 3), align 1
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%1 = load i8, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @bArray, i32 0, i32 5), align 1
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%conv2 = sext i8 %1 to i32
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%sub3 = sub nsw i32 %conv2, 7
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%conv4 = trunc i32 %sub3 to i8
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store i8 %conv4, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @bArray, i32 0, i32 3), align 1
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%2 = load i16, i16* getelementptr inbounds ([13 x i16], [13 x i16]* @hArray, i32 0, i32 5), align 2
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%conv5 = sext i16 %2 to i32
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%sub6 = sub nsw i32 %conv5, 7
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%conv7 = trunc i32 %sub6 to i16
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store i16 %conv7, i16* getelementptr inbounds ([13 x i16], [13 x i16]* @hArray, i32 0, i32 3), align 2
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%3 = load i16, i16* getelementptr inbounds ([13 x i16], [13 x i16]* @hArray, i32 0, i32 5), align 2
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%conv8 = sext i16 %3 to i32
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%sub9 = sub nsw i32 %conv8, 7
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%conv10 = trunc i32 %sub9 to i16
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store i16 %conv10, i16* getelementptr inbounds ([13 x i16], [13 x i16]* @hArray, i32 0, i32 3), align 2
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%4 = load i32, i32* getelementptr inbounds ([13 x i32], [13 x i32]* @wArray, i32 0, i32 5), align 4
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%sub11 = sub nsw i32 %4, 7
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store i32 %sub11, i32* getelementptr inbounds ([13 x i32], [13 x i32]* @wArray, i32 0, i32 3), align 4
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ret void
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}
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; Function Attrs: noinline nounwind optnone
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define i32 @_Z3barPi(i32* %z) {
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entry:
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%z.addr = alloca i32*, align 4
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store i32* %z, i32** %z.addr, align 4
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%0 = load i32*, i32** %z.addr, align 4
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fence seq_cst
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%1 = atomicrmw add i32* %0, i32 42 monotonic
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fence seq_cst
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%2 = add i32 %1, 42
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ret i32 %2
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}
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...
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---
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name: _Z3foov
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr32, preferred-register: '' }
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- { id: 1, class: gpr32, preferred-register: '' }
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- { id: 2, class: gpr32, preferred-register: '' }
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- { id: 3, class: gpr32, preferred-register: '' }
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- { id: 4, class: gpr32, preferred-register: '' }
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- { id: 5, class: gpr32, preferred-register: '' }
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- { id: 6, class: gpr32, preferred-register: '' }
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- { id: 7, class: gpr32, preferred-register: '' }
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- { id: 8, class: gpr32, preferred-register: '' }
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- { id: 9, class: gpr32, preferred-register: '' }
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- { id: 10, class: gpr32, preferred-register: '' }
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- { id: 11, class: gpr32, preferred-register: '' }
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- { id: 12, class: gpr32, preferred-register: '' }
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- { id: 13, class: gpr32, preferred-register: '' }
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- { id: 14, class: gpr32, preferred-register: '' }
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- { id: 15, class: gpr32, preferred-register: '' }
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liveins:
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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bb.0.entry:
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%0:gpr32 = LUi target-flags(mips-abs-hi) @bArray
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%1:gpr32 = ADDiu killed %0, target-flags(mips-abs-lo) @bArray
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%2:gpr32 = LBuE %1, 5 :: (dereferenceable load 1 from `i8* getelementptr inbounds ([13 x i8], [13 x i8]* @bArray, i32 0, i32 5)`)
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%3:gpr32 = ADDiu killed %2, -7
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SBE killed %3, %1, 3 :: (store 1 into `i8* getelementptr inbounds ([13 x i8], [13 x i8]* @bArray, i32 0, i32 3)`)
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%4:gpr32 = LBE %1, 5 :: (dereferenceable load 1 from `i8* getelementptr inbounds ([13 x i8], [13 x i8]* @bArray, i32 0, i32 5)`)
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%5:gpr32 = ADDiu killed %4, -7
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SBE killed %5, %1, 3 :: (store 1 into `i8* getelementptr inbounds ([13 x i8], [13 x i8]* @bArray, i32 0, i32 3)`)
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%6:gpr32 = LUi target-flags(mips-abs-hi) @hArray
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%7:gpr32 = ADDiu killed %6, target-flags(mips-abs-lo) @hArray
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%8:gpr32 = LHuE %7, 10 :: (dereferenceable load 2 from `i16* getelementptr inbounds ([13 x i16], [13 x i16]* @hArray, i32 0, i32 5)`)
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%9:gpr32 = ADDiu killed %8, -7
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SHE killed %9, %7, 6 :: (store 2 into `i16* getelementptr inbounds ([13 x i16], [13 x i16]* @hArray, i32 0, i32 3)`)
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%10:gpr32 = LHE %7, 10 :: (dereferenceable load 2 from `i16* getelementptr inbounds ([13 x i16], [13 x i16]* @hArray, i32 0, i32 5)`)
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%11:gpr32 = ADDiu killed %10, -7
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SHE killed %11, %7, 6 :: (store 2 into `i16* getelementptr inbounds ([13 x i16], [13 x i16]* @hArray, i32 0, i32 3)`)
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%12:gpr32 = LUi target-flags(mips-abs-hi) @wArray
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%13:gpr32 = ADDiu killed %12, target-flags(mips-abs-lo) @wArray
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%14:gpr32 = LWE %13, 20 :: (dereferenceable load 4 from `i32* getelementptr inbounds ([13 x i32], [13 x i32]* @wArray, i32 0, i32 5)`)
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%15:gpr32 = ADDiu killed %14, -7
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SWE killed %15, %13, 12 :: (store 4 into `i32* getelementptr inbounds ([13 x i32], [13 x i32]* @wArray, i32 0, i32 3)`)
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RetRA
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...
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---
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name: _Z3barPi
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr32, preferred-register: '' }
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- { id: 1, class: gpr32, preferred-register: '' }
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- { id: 2, class: gpr32, preferred-register: '' }
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- { id: 3, class: gpr32, preferred-register: '' }
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- { id: 4, class: gpr32, preferred-register: '' }
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- { id: 5, class: gpr32, preferred-register: '' }
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- { id: 6, class: gpr32, preferred-register: '' }
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- { id: 7, class: gpr32, preferred-register: '' }
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- { id: 8, class: gpr32, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$a0', virtual-reg: '%0' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 4
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 4294967295
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
- { id: 0, name: z.addr, type: default, offset: 0, size: 4, alignment: 4,
|
||||
stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
|
||||
di-variable: '', di-expression: '', di-location: '' }
|
||||
constants:
|
||||
body: |
|
||||
bb.0.entry:
|
||||
successors: %bb.1(0x80000000)
|
||||
liveins: $a0
|
||||
|
||||
%0:gpr32 = COPY $a0
|
||||
%1:gpr32 = COPY %0
|
||||
SW %0, %stack.0.z.addr, 0 :: (store 4 into %ir.z.addr)
|
||||
%2:gpr32 = LW %stack.0.z.addr, 0 :: (dereferenceable load 4 from %ir.z.addr)
|
||||
SYNC 0
|
||||
%3:gpr32 = ADDiu $zero, 42
|
||||
|
||||
bb.1.entry:
|
||||
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
|
||||
%4:gpr32 = LLE %2, 0
|
||||
%6:gpr32 = ADDu %4, %3
|
||||
%8:gpr32 = SCE %6, %2, 0
|
||||
BEQ %8, $zero, %bb.1, implicit-def $at
|
||||
|
||||
bb.2.entry:
|
||||
SYNC 0
|
||||
%5:gpr32 = ADDiu killed %4, 42
|
||||
$v0 = COPY %5
|
||||
CACHEE %1, 5, 2
|
||||
PREFE %1, 5, 2
|
||||
RetRA implicit $v0
|
||||
|
||||
...
|
||||
|
||||
# CHECK: 60 41 60 05 lbue $2, 5($1)
|
||||
# CHECK: 60 41 68 05 lbe $2, 5($1)
|
||||
# CHECK: 60 41 a8 03 sbe $2, 3($1)
|
||||
|
||||
# CHECK: 60 41 62 0a lhue $2, 10($1)
|
||||
# CHECK: 60 41 6a 0a lhe $2, 10($1)
|
||||
# CHECK: 60 41 aa 06 she $2, 6($1)
|
||||
|
||||
# CHECK: 60 41 6e 14 lwe $2, 20($1)
|
||||
# CHECK: 60 41 ae 0c swe $2, 12($1)
|
||||
|
||||
# CHECK: 60 41 6c 00 lle $2, 0($1)
|
||||
# CHECK: 60 81 ac 00 sce $4, 0($1)
|
||||
|
||||
# CHECK: 60 41 a6 05 cachee 2, 5($1)
|
||||
# CHECK: 60 41 a4 05 prefe 2, 5($1)
|
||||
Loading…
Reference in New Issue