From a316faabecda004e6607ad16e4e9020e4bc55e4b Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Wed, 7 Mar 2012 23:00:52 +0000 Subject: [PATCH] misched prep: rename InsertPos to End. ScheduleDAGInstrs knows nothing about how instructions will be moved or inserted. llvm-svn: 152256 --- llvm/lib/CodeGen/MachineScheduler.cpp | 2 +- llvm/lib/CodeGen/PostRASchedulerList.cpp | 16 ++++++++-------- llvm/lib/CodeGen/ScheduleDAGInstrs.cpp | 10 +++++----- llvm/lib/CodeGen/ScheduleDAGInstrs.h | 14 ++++++-------- 4 files changed, 20 insertions(+), 22 deletions(-) diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index 39a1e6625691..cf6af4bfdef7 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -226,7 +226,7 @@ void ScheduleTopDownLive::schedule() { releaseNode(&(*I)); } - InsertPos = Begin; + MachineBasicBlock::iterator InsertPos = Begin; while (SUnit *SU = pickNode()) { DEBUG(dbgs() << "*** Scheduling Instruction:\n"; SU->dump(this)); diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp index cec3223ff3a4..c00cf0e0439c 100644 --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp @@ -365,8 +365,8 @@ void SchedulePostRATDList::schedule() { if (AntiDepBreak != NULL) { unsigned Broken = - AntiDepBreak->BreakAntiDependencies(SUnits, Begin, InsertPos, - InsertPosIndex, DbgValues); + AntiDepBreak->BreakAntiDependencies(SUnits, Begin, End, EndIndex, + DbgValues); if (Broken != 0) { // We made changes. Update the dependency graph. @@ -396,7 +396,7 @@ void SchedulePostRATDList::schedule() { /// void SchedulePostRATDList::Observe(MachineInstr *MI, unsigned Count) { if (AntiDepBreak != NULL) - AntiDepBreak->Observe(MI, Count, InsertPosIndex); + AntiDepBreak->Observe(MI, Count, EndIndex); } /// FinishBlock - Clean up register live-range state. @@ -761,24 +761,24 @@ void SchedulePostRATDList::ListScheduleTopDown() { // EmitSchedule - Emit the machine code in scheduled order. void SchedulePostRATDList::EmitSchedule() { - Begin = InsertPos; + Begin = End; // If first instruction was a DBG_VALUE then put it back. if (FirstDbgValue) - BB->splice(InsertPos, BB, FirstDbgValue); + BB->splice(End, BB, FirstDbgValue); // Then re-insert them according to the given schedule. for (unsigned i = 0, e = Sequence.size(); i != e; i++) { if (SUnit *SU = Sequence[i]) - BB->splice(InsertPos, BB, SU->getInstr()); + BB->splice(End, BB, SU->getInstr()); else // Null SUnit* is a noop. - TII->insertNoop(*BB, InsertPos); + TII->insertNoop(*BB, End); // Update the Begin iterator, as the first instruction in the block // may have been scheduled later. if (i == 0) - Begin = prior(InsertPos); + Begin = prior(End); } // Reinsert any remaining debug_values. diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp index ef63776d6e23..505d56c79ec1 100644 --- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -160,8 +160,8 @@ void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb, unsigned endcount) { BB = bb; Begin = begin; - InsertPos = end; - InsertPosIndex = endcount; + End = end; + EndIndex = endcount; // Check to see if the scheduler cares about latencies. UnitLatencies = forceUnitLatencies(); @@ -184,7 +184,7 @@ void ScheduleDAGInstrs::exitRegion() { /// are too high to be hidden by the branch or when the liveout registers /// used by instructions in the fallthrough block. void ScheduleDAGInstrs::addSchedBarrierDeps() { - MachineInstr *ExitMI = InsertPos != BB->end() ? &*InsertPos : 0; + MachineInstr *ExitMI = End != BB->end() ? &*End : 0; ExitSU.setInstr(ExitMI); bool AllDepKnown = ExitMI && (ExitMI->isCall() || ExitMI->isBarrier()); @@ -476,7 +476,7 @@ void ScheduleDAGInstrs::initSUnits() { // which is contained within a basic block. SUnits.reserve(BB->size()); - for (MachineBasicBlock::iterator I = Begin; I != InsertPos; ++I) { + for (MachineBasicBlock::iterator I = Begin; I != End; ++I) { MachineInstr *MI = I; if (MI->isDebugValue()) continue; @@ -534,7 +534,7 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA) { // Walk the list of instructions, from bottom moving up. MachineInstr *PrevMI = NULL; - for (MachineBasicBlock::iterator MII = InsertPos, MIE = Begin; + for (MachineBasicBlock::iterator MII = End, MIE = Begin; MII != MIE; --MII) { MachineInstr *MI = prior(MII); if (MI && PrevMI) { diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.h b/llvm/lib/CodeGen/ScheduleDAGInstrs.h index 91b7350ab1f8..ace97d8ff85c 100644 --- a/llvm/lib/CodeGen/ScheduleDAGInstrs.h +++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.h @@ -119,16 +119,14 @@ namespace llvm { // The block in which to insert instructions MachineBasicBlock *BB; - // The beginning of the range to - // be scheduled. The range extends - // to InsertPos. + /// The beginning of the range to be scheduled. MachineBasicBlock::iterator Begin; - // The position to insert instructions - MachineBasicBlock::iterator InsertPos; + /// The end of the range to be scheduled. + MachineBasicBlock::iterator End; - // The index in BB of InsertPos. - unsigned InsertPosIndex; + /// The index in BB of End. + unsigned EndIndex; /// After calling BuildSchedGraph, each machine instruction in the current /// scheduling region is mapped to an SUnit. @@ -239,7 +237,7 @@ namespace llvm { MachineBasicBlock::iterator begin() const { return Begin; } /// end - Return an iterator to the bottom of the current scheduling region. - MachineBasicBlock::iterator end() const { return InsertPos; } + MachineBasicBlock::iterator end() const { return End; } /// NewSUnit - Creates a new SUnit and return a ptr to it. ///