forked from OSchip/llvm-project
[X86] Use the same predicate for the load for PMOVSXBQ and PMOVZXBQ.
These both use a 16-bit load, but one used loadi16_anyext and the other used extloadi32i16. The only difference between them is that loadi16_anyext checked that the load was at least 2 byte aligned and non-volatile. But the alignment doesn't matter here. Just use extloadi32i16 for both. llvm-svn: 329154
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@ -8548,7 +8548,7 @@ defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, sext_invec, "s", A
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multiclass AVX512_pmovx_patterns<string OpcPrefix, SDNode ExtOp,
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SDNode InVecOp, PatFrag ExtLoad16> {
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SDNode InVecOp> {
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// 128-bit patterns
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let Predicates = [HasVLX, HasBWI] in {
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def : Pat<(v8i16 (InVecOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
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@ -8572,7 +8572,7 @@ multiclass AVX512_pmovx_patterns<string OpcPrefix, SDNode ExtOp,
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def : Pat<(v4i32 (InVecOp (bc_v16i8 (loadv2i64 addr:$src)))),
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(!cast<I>(OpcPrefix#BDZ128rm) addr:$src)>;
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def : Pat<(v2i64 (InVecOp (bc_v16i8 (v4i32 (scalar_to_vector (ExtLoad16 addr:$src)))))),
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def : Pat<(v2i64 (InVecOp (bc_v16i8 (v4i32 (scalar_to_vector (extloadi32i16 addr:$src)))))),
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(!cast<I>(OpcPrefix#BQZ128rm) addr:$src)>;
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def : Pat<(v2i64 (InVecOp (v16i8 (vzmovl_v4i32 addr:$src)))),
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(!cast<I>(OpcPrefix#BQZ128rm) addr:$src)>;
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@ -8688,8 +8688,8 @@ multiclass AVX512_pmovx_patterns<string OpcPrefix, SDNode ExtOp,
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}
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}
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defm : AVX512_pmovx_patterns<"VPMOVSX", X86vsext, sext_invec, extloadi32i16>;
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defm : AVX512_pmovx_patterns<"VPMOVZX", X86vzext, zext_invec, loadi16_anyext>;
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defm : AVX512_pmovx_patterns<"VPMOVSX", X86vsext, sext_invec>;
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defm : AVX512_pmovx_patterns<"VPMOVZX", X86vzext, zext_invec>;
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//===----------------------------------------------------------------------===//
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// GATHER - SCATTER Operations
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@ -1061,14 +1061,6 @@ def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
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return false;
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}]>;
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def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
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LoadSDNode *LD = cast<LoadSDNode>(N);
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ISD::LoadExtType ExtType = LD->getExtensionType();
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if (ExtType == ISD::EXTLOAD)
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return LD->getAlignment() >= 2 && !LD->isVolatile();
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return false;
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}]>;
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def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
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LoadSDNode *LD = cast<LoadSDNode>(N);
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ISD::LoadExtType ExtType = LD->getExtensionType();
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@ -5473,7 +5473,7 @@ defm : SS41I_pmovx_avx2_patterns<"VPMOVZX", "z", X86vzext>;
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// SSE4.1/AVX patterns.
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multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy,
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SDNode ExtOp, PatFrag ExtLoad16> {
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SDNode ExtOp> {
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let Predicates = [HasAVX, NoVLX_Or_NoBWI] in {
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def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))),
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(!cast<I>(OpcPrefix#BWrr) VR128:$src)>;
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@ -5532,7 +5532,7 @@ multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy,
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def : Pat<(v4i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
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(!cast<I>(OpcPrefix#BDrm) addr:$src)>;
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def : Pat<(v2i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (ExtLoad16 addr:$src)))))),
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def : Pat<(v2i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (extloadi32i16 addr:$src)))))),
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(!cast<I>(OpcPrefix#BQrm) addr:$src)>;
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def : Pat<(v2i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
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(!cast<I>(OpcPrefix#BQrm) addr:$src)>;
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@ -5574,12 +5574,12 @@ multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy,
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}
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}
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defm : SS41I_pmovx_patterns<"VPMOVSX", "s", sext_invec, extloadi32i16>;
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defm : SS41I_pmovx_patterns<"VPMOVZX", "z", zext_invec, loadi16_anyext>;
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defm : SS41I_pmovx_patterns<"VPMOVSX", "s", sext_invec>;
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defm : SS41I_pmovx_patterns<"VPMOVZX", "z", zext_invec>;
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let Predicates = [UseSSE41] in {
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defm : SS41I_pmovx_patterns<"PMOVSX", "s", sext_invec, extloadi32i16>;
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defm : SS41I_pmovx_patterns<"PMOVZX", "z", zext_invec, loadi16_anyext>;
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defm : SS41I_pmovx_patterns<"PMOVSX", "s", sext_invec>;
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defm : SS41I_pmovx_patterns<"PMOVZX", "z", zext_invec>;
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}
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//===----------------------------------------------------------------------===//
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