diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 889f05ae5d55..fba3c99a767d 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -8548,7 +8548,7 @@ defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, sext_invec, "s", A multiclass AVX512_pmovx_patterns<string OpcPrefix, SDNode ExtOp, - SDNode InVecOp, PatFrag ExtLoad16> { + SDNode InVecOp> { // 128-bit patterns let Predicates = [HasVLX, HasBWI] in { def : Pat<(v8i16 (InVecOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), @@ -8572,7 +8572,7 @@ multiclass AVX512_pmovx_patterns<string OpcPrefix, SDNode ExtOp, def : Pat<(v4i32 (InVecOp (bc_v16i8 (loadv2i64 addr:$src)))), (!cast<I>(OpcPrefix#BDZ128rm) addr:$src)>; - def : Pat<(v2i64 (InVecOp (bc_v16i8 (v4i32 (scalar_to_vector (ExtLoad16 addr:$src)))))), + def : Pat<(v2i64 (InVecOp (bc_v16i8 (v4i32 (scalar_to_vector (extloadi32i16 addr:$src)))))), (!cast<I>(OpcPrefix#BQZ128rm) addr:$src)>; def : Pat<(v2i64 (InVecOp (v16i8 (vzmovl_v4i32 addr:$src)))), (!cast<I>(OpcPrefix#BQZ128rm) addr:$src)>; @@ -8688,8 +8688,8 @@ multiclass AVX512_pmovx_patterns<string OpcPrefix, SDNode ExtOp, } } -defm : AVX512_pmovx_patterns<"VPMOVSX", X86vsext, sext_invec, extloadi32i16>; -defm : AVX512_pmovx_patterns<"VPMOVZX", X86vzext, zext_invec, loadi16_anyext>; +defm : AVX512_pmovx_patterns<"VPMOVSX", X86vsext, sext_invec>; +defm : AVX512_pmovx_patterns<"VPMOVZX", X86vzext, zext_invec>; //===----------------------------------------------------------------------===// // GATHER - SCATTER Operations diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index 04894e199dd9..f7a9fd756e31 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -1061,14 +1061,6 @@ def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ return false; }]>; -def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{ - LoadSDNode *LD = cast<LoadSDNode>(N); - ISD::LoadExtType ExtType = LD->getExtensionType(); - if (ExtType == ISD::EXTLOAD) - return LD->getAlignment() >= 2 && !LD->isVolatile(); - return false; -}]>; - def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ LoadSDNode *LD = cast<LoadSDNode>(N); ISD::LoadExtType ExtType = LD->getExtensionType(); diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index bf627ad57743..863ec6d11099 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -5473,7 +5473,7 @@ defm : SS41I_pmovx_avx2_patterns<"VPMOVZX", "z", X86vzext>; // SSE4.1/AVX patterns. multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy, - SDNode ExtOp, PatFrag ExtLoad16> { + SDNode ExtOp> { let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))), (!cast<I>(OpcPrefix#BWrr) VR128:$src)>; @@ -5532,7 +5532,7 @@ multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy, def : Pat<(v4i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))), (!cast<I>(OpcPrefix#BDrm) addr:$src)>; - def : Pat<(v2i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (ExtLoad16 addr:$src)))))), + def : Pat<(v2i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (extloadi32i16 addr:$src)))))), (!cast<I>(OpcPrefix#BQrm) addr:$src)>; def : Pat<(v2i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))), (!cast<I>(OpcPrefix#BQrm) addr:$src)>; @@ -5574,12 +5574,12 @@ multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy, } } -defm : SS41I_pmovx_patterns<"VPMOVSX", "s", sext_invec, extloadi32i16>; -defm : SS41I_pmovx_patterns<"VPMOVZX", "z", zext_invec, loadi16_anyext>; +defm : SS41I_pmovx_patterns<"VPMOVSX", "s", sext_invec>; +defm : SS41I_pmovx_patterns<"VPMOVZX", "z", zext_invec>; let Predicates = [UseSSE41] in { - defm : SS41I_pmovx_patterns<"PMOVSX", "s", sext_invec, extloadi32i16>; - defm : SS41I_pmovx_patterns<"PMOVZX", "z", zext_invec, loadi16_anyext>; + defm : SS41I_pmovx_patterns<"PMOVSX", "s", sext_invec>; + defm : SS41I_pmovx_patterns<"PMOVZX", "z", zext_invec>; } //===----------------------------------------------------------------------===//