forked from OSchip/llvm-project
[X86] Remove ReadAfterLd from several several rb instructions
This affects CVTSD2SS, FMA, RCP28, RSQRT28, and SQRT scalar instructions 'b' here refers to 'sae' not broadcast. These aren't memory instructions. llvm-svn: 320281
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@ -6250,7 +6250,7 @@ let Constraints = "$src1 = $dst", hasSideEffects = 0 in {
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(ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
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OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb,
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NoItinerary, 1, 1>, AVX512FMA3Base, EVEX_B, EVEX_RC,
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Sched<[WriteFMA, ReadAfterLd]>;
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Sched<[WriteFMA]>;
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let isCodeGenOnly = 1, isCommutable = 1 in {
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def r : AVX512FMA3S<opc, MRMSrcReg, (outs _.FRC:$dst),
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@ -6790,8 +6790,8 @@ multiclass avx512_cvt_fp_rc_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInf
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"$rc, $src2, $src1", "$src1, $src2, $rc",
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(_.VT (OpNodeRnd (_.VT _.RC:$src1),
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(_Src.VT _Src.RC:$src2), (i32 imm:$rc))),
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itins.rm>,
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EVEX_4V, VEX_LIG, Sched<[itins.Sched.Folded, ReadAfterLd]>,
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itins.rr>,
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EVEX_4V, VEX_LIG, Sched<[itins.Sched]>,
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EVEX_B, EVEX_RC;
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}
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multiclass avx512_cvt_fp_scalar_sd2ss<bits<8> opc, string OpcodeStr,
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@ -7743,7 +7743,7 @@ multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
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"{sae}, $src2, $src1", "$src1, $src2, {sae}",
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(OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
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(i32 FROUND_NO_EXC)), itins.rm>, EVEX_B,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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Sched<[itins.Sched]>;
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defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.IntScalarMemOp:$src2), OpcodeStr,
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@ -7923,7 +7923,7 @@ multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr, OpndItins itins,
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(X86fsqrtRnds (_.VT _.RC:$src1),
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(_.VT _.RC:$src2),
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(i32 imm:$rc)), itins.rr>,
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EVEX_B, EVEX_RC, Sched<[itins.Sched.Folded, ReadAfterLd]>;
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EVEX_B, EVEX_RC, Sched<[itins.Sched]>;
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let isCodeGenOnly = 1, hasSideEffects = 0 in {
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def r : I<opc, MRMSrcReg, (outs _.FRC:$dst),
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