maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

clean up the memory management of the operands. 

llvm-svn: 93526
This commit is contained in:
Chris Lattner 2010-01-15 18:44:13 +00:00
parent 9751396d70
commit a2bbb7cbc6
1 changed files with 52 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

105
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
View File

@ -39,9 +39,8 @@ private:
bool ParseRegister(unsigned &RegNo); bool ParseRegister(unsigned &RegNo);
bool ParseOperand(X86Operand &Op); X86Operand *ParseOperand();
X86Operand *ParseMemOperand();
bool ParseMemOperand(X86Operand &Op);
bool ParseDirectiveWord(unsigned Size, SMLoc L); bool ParseDirectiveWord(unsigned Size, SMLoc L);
@ -200,23 +199,23 @@ struct X86Operand : public MCParsedAsmOperand {
return Res; return Res;
} }
static X86Operand CreateReg(unsigned RegNo) { static X86Operand *CreateReg(unsigned RegNo) {
X86Operand Res; X86Operand Res;
Res.Kind = Register; Res.Kind = Register;
Res.Reg.RegNo = RegNo; Res.Reg.RegNo = RegNo;
return Res; return new X86Operand(Res);
} }
static X86Operand CreateImm(const MCExpr *Val) { static X86Operand *CreateImm(const MCExpr *Val) {
X86Operand Res; X86Operand Res;
Res.Kind = Immediate; Res.Kind = Immediate;
Res.Imm.Val = Val; Res.Imm.Val = Val;
return Res; return new X86Operand(Res);
} }
static X86Operand CreateMem(unsigned SegReg, const MCExpr *Disp, static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
unsigned BaseReg, unsigned IndexReg, unsigned BaseReg, unsigned IndexReg,
unsigned Scale) { unsigned Scale) {
// We should never just have a displacement, that would be an immediate. // We should never just have a displacement, that would be an immediate.
assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!"); assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
@ -230,7 +229,7 @@ struct X86Operand : public MCParsedAsmOperand {
Res.Mem.BaseReg = BaseReg; Res.Mem.BaseReg = BaseReg;
Res.Mem.IndexReg = IndexReg; Res.Mem.IndexReg = IndexReg;
Res.Mem.Scale = Scale; Res.Mem.Scale = Scale;
return Res; return new X86Operand(Res);
} }
}; };
@ -259,32 +258,30 @@ bool X86ATTAsmParser::ParseRegister(unsigned &RegNo) {
return false; return false;
} }
bool X86ATTAsmParser::ParseOperand(X86Operand &Op) { X86Operand *X86ATTAsmParser::ParseOperand() {
switch (getLexer().getKind()) { switch (getLexer().getKind()) {
default: default:
return ParseMemOperand(Op); return ParseMemOperand();
case AsmToken::Percent: { case AsmToken::Percent: {
// FIXME: if a segment register, this could either be just the seg reg, or // FIXME: if a segment register, this could either be just the seg reg, or
// the start of a memory operand. // the start of a memory operand.
unsigned RegNo; unsigned RegNo;
if (ParseRegister(RegNo)) return true; if (ParseRegister(RegNo)) return 0;
Op = X86Operand::CreateReg(RegNo); return X86Operand::CreateReg(RegNo);
return false;
} }
case AsmToken::Dollar: { case AsmToken::Dollar: {
// $42 -> immediate. // $42 -> immediate.
getLexer().Lex(); getLexer().Lex();
const MCExpr *Val; const MCExpr *Val;
if (getParser().ParseExpression(Val)) if (getParser().ParseExpression(Val))
return true; return 0;
Op = X86Operand::CreateImm(Val); return X86Operand::CreateImm(Val);
return false;
} }
} }
} }
/// ParseMemOperand: segment: disp(basereg, indexreg, scale) /// ParseMemOperand: segment: disp(basereg, indexreg, scale)
bool X86ATTAsmParser::ParseMemOperand(X86Operand &Op) { X86Operand *X86ATTAsmParser::ParseMemOperand() {
// FIXME: If SegReg ':' (e.g. %gs:), eat and remember. // FIXME: If SegReg ':' (e.g. %gs:), eat and remember.
unsigned SegReg = 0; unsigned SegReg = 0;
@ -294,17 +291,15 @@ bool X86ATTAsmParser::ParseMemOperand(X86Operand &Op) {
// it. // it.
const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext()); const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
if (getLexer().isNot(AsmToken::LParen)) { if (getLexer().isNot(AsmToken::LParen)) {
if (getParser().ParseExpression(Disp)) return true; if (getParser().ParseExpression(Disp)) return 0;
// After parsing the base expression we could either have a parenthesized // After parsing the base expression we could either have a parenthesized
// memory address or not. If not, return now. If so, eat the (. // memory address or not. If not, return now. If so, eat the (.
if (getLexer().isNot(AsmToken::LParen)) { if (getLexer().isNot(AsmToken::LParen)) {
// Unless we have a segment register, treat this as an immediate. // Unless we have a segment register, treat this as an immediate.
if (SegReg) if (SegReg == 0)
Op = X86Operand::CreateMem(SegReg, Disp, 0, 0, 1); return X86Operand::CreateImm(Disp);
else return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1);
Op = X86Operand::CreateImm(Disp);
return false;
} }
// Eat the '('. // Eat the '('.
@ -320,17 +315,15 @@ bool X86ATTAsmParser::ParseMemOperand(X86Operand &Op) {
} else { } else {
// It must be an parenthesized expression, parse it now. // It must be an parenthesized expression, parse it now.
if (getParser().ParseParenExpression(Disp)) if (getParser().ParseParenExpression(Disp))
return true; return 0;
// After parsing the base expression we could either have a parenthesized // After parsing the base expression we could either have a parenthesized
// memory address or not. If not, return now. If so, eat the (. // memory address or not. If not, return now. If so, eat the (.
if (getLexer().isNot(AsmToken::LParen)) { if (getLexer().isNot(AsmToken::LParen)) {
// Unless we have a segment register, treat this as an immediate. // Unless we have a segment register, treat this as an immediate.
if (SegReg) if (SegReg == 0)
Op = X86Operand::CreateMem(SegReg, Disp, 0, 0, 1); return X86Operand::CreateImm(Disp);
else return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1);
Op = X86Operand::CreateImm(Disp);
return false;
} }
// Eat the '('. // Eat the '('.
@ -343,7 +336,7 @@ bool X86ATTAsmParser::ParseMemOperand(X86Operand &Op) {
unsigned BaseReg = 0, IndexReg = 0, Scale = 1; unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
if (getLexer().is(AsmToken::Percent)) if (getLexer().is(AsmToken::Percent))
if (ParseRegister(BaseReg)) return true; if (ParseRegister(BaseReg)) return 0;
if (getLexer().is(AsmToken::Comma)) { if (getLexer().is(AsmToken::Comma)) {
getLexer().Lex(); // Eat the comma. getLexer().Lex(); // Eat the comma.
@ -355,13 +348,16 @@ bool X86ATTAsmParser::ParseMemOperand(X86Operand &Op) {
// Not that even though it would be completely consistent to support syntax // Not that even though it would be completely consistent to support syntax
// like "1(%eax,,1)", the assembler doesn't. // like "1(%eax,,1)", the assembler doesn't.
if (getLexer().is(AsmToken::Percent)) { if (getLexer().is(AsmToken::Percent)) {
if (ParseRegister(IndexReg)) return true; if (ParseRegister(IndexReg)) return 0;
if (getLexer().isNot(AsmToken::RParen)) { if (getLexer().isNot(AsmToken::RParen)) {
// Parse the scale amount: // Parse the scale amount:
// ::= ',' [scale-expression] // ::= ',' [scale-expression]
if (getLexer().isNot(AsmToken::Comma)) if (getLexer().isNot(AsmToken::Comma)) {
return true; Error(getLexer().getTok().getLoc(),
"expected comma in scale expression");
return 0;
}
getLexer().Lex(); // Eat the comma. getLexer().Lex(); // Eat the comma.
if (getLexer().isNot(AsmToken::RParen)) { if (getLexer().isNot(AsmToken::RParen)) {
@ -369,11 +365,13 @@ bool X86ATTAsmParser::ParseMemOperand(X86Operand &Op) {
int64_t ScaleVal; int64_t ScaleVal;
if (getParser().ParseAbsoluteExpression(ScaleVal)) if (getParser().ParseAbsoluteExpression(ScaleVal))
return true; return 0;
// Validate the scale amount. // Validate the scale amount.
if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8) if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
return Error(Loc, "scale factor in address must be 1, 2, 4 or 8"); Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
return 0;
}
Scale = (unsigned)ScaleVal; Scale = (unsigned)ScaleVal;
} }
} }
@ -384,20 +382,21 @@ bool X86ATTAsmParser::ParseMemOperand(X86Operand &Op) {
int64_t Value; int64_t Value;
if (getParser().ParseAbsoluteExpression(Value)) if (getParser().ParseAbsoluteExpression(Value))
return true; return 0;
return Error(Loc, "cannot have scale factor without index register"); Error(Loc, "cannot have scale factor without index register");
return 0;
} }
} }
// Ok, we've eaten the memory operand, verify we have a ')' and eat it too. // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
if (getLexer().isNot(AsmToken::RParen)) if (getLexer().isNot(AsmToken::RParen)) {
return Error(getLexer().getTok().getLoc(), Error(getLexer().getTok().getLoc(), "unexpected token in memory operand");
"unexpected token in memory operand"); return 0;
}
getLexer().Lex(); // Eat the ')'. getLexer().Lex(); // Eat the ')'.
Op = X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale); return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale);
return false;
} }
bool X86ATTAsmParser:: bool X86ATTAsmParser::
@ -416,19 +415,19 @@ ParseInstruction(const StringRef &Name, SMLoc NameLoc,
} }
// Read the first operand. // Read the first operand.
X86Operand Op; if (X86Operand *Op = ParseOperand())
if (ParseOperand(Op)) Operands.push_back(Op);
else
return true; return true;
Operands.push_back(new X86Operand(Op));
while (getLexer().is(AsmToken::Comma)) { while (getLexer().is(AsmToken::Comma)) {
getLexer().Lex(); // Eat the comma. getLexer().Lex(); // Eat the comma.
// Parse and remember the operand. // Parse and remember the operand.
if (ParseOperand(Op)) if (X86Operand *Op = ParseOperand())
Operands.push_back(Op);
else
return true; return true;
Operands.push_back(new X86Operand(Op));
} }
} }