forked from OSchip/llvm-project
[GISel] Eliminate redundant bitmasking
This was a GISel vs SDAG regression that showed up at -Os on arm64 in: SingleSource/Benchmarks/Adobe-C++/simple_types_constant_folding.test https://llvm.godbolt.org/z/aecjodsjG Differential revision: https://reviews.llvm.org/D103334
This commit is contained in:
Jon Roelofs
parent
7b06120882
commit
a2ab765029
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@ -435,6 +435,11 @@ public:
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std::tuple<Register, int64_t> &MatchInfo);
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bool applyAshShlToSextInreg(MachineInstr &MI,
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std::tuple<Register, int64_t> &MatchInfo);
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/// Fold and(and(x, C1), C2) -> C1&C2 ? and(x, C1&C2) : 0
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bool matchOverlappingAnd(MachineInstr &MI,
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std::function<void(MachineIRBuilder &)> &MatchInfo);
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/// \return true if \p MI is a G_AND instruction whose operands are x and y
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/// where x & y == x or x & y == y. (E.g., one of operands is all-ones value.)
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///
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@ -402,6 +402,15 @@ def shl_ashr_to_sext_inreg : GICombineRule<
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[{ return Helper.matchAshrShlToSextInreg(*${root}, ${info}); }]),
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(apply [{ return Helper.applyAshShlToSextInreg(*${root}, ${info});}])
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>;
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// Fold and(and(x, C1), C2) -> C1&C2 ? and(x, C1&C2) : 0
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def overlapping_and: GICombineRule <
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(defs root:$root, build_fn_matchinfo:$info),
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(match (wip_match_opcode G_AND):$root,
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[{ return Helper.matchOverlappingAnd(*${root}, ${info}); }]),
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(apply [{ return Helper.applyBuildFn(*${root}, ${info}); }])
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>;
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// Fold (x & y) -> x or (x & y) -> y when (x & y) is known to equal x or equal y.
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def redundant_and: GICombineRule <
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(defs root:$root, register_matchinfo:$matchinfo),
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@ -643,7 +652,8 @@ def identity_combines : GICombineGroup<[select_same_val, right_identity_zero,
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i2p_to_p2i, anyext_trunc_fold,
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fneg_fneg_fold, right_identity_one]>;
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def const_combines : GICombineGroup<[constant_fp_op, const_ptradd_to_i2p]>;
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def const_combines : GICombineGroup<[constant_fp_op, const_ptradd_to_i2p,
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overlapping_and]>;
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def known_bits_simplifications : GICombineGroup<[
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redundant_and, redundant_sext_inreg, redundant_or, urem_pow2_to_mask,
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@ -2997,6 +2997,33 @@ bool CombinerHelper::applyAshShlToSextInreg(
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return true;
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}
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/// and(and(x, C1), C2) -> C1&C2 ? and(x, C1&C2) : 0
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bool CombinerHelper::matchOverlappingAnd(
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MachineInstr &MI, std::function<void(MachineIRBuilder &)> &MatchInfo) {
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assert(MI.getOpcode() == TargetOpcode::G_AND);
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Register Dst = MI.getOperand(0).getReg();
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LLT Ty = MRI.getType(Dst);
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Register R;
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int64_t C1;
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int64_t C2;
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if (!mi_match(
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Dst, MRI,
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m_GAnd(m_GAnd(m_Reg(R), m_ICst(C1)), m_ICst(C2))))
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return false;
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MatchInfo = [=](MachineIRBuilder &B) {
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if (C1 & C2) {
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B.buildAnd(Dst, R, B.buildConstant(Ty, C1 & C2));
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return;
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}
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auto Zero = B.buildConstant(Ty, 0);
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replaceRegWith(MRI, Dst, Zero->getOperand(0).getReg());
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};
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return true;
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}
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bool CombinerHelper::matchRedundantAnd(MachineInstr &MI,
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Register &Replacement) {
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// Given
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@ -0,0 +1,121 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -debugify-and-strip-all-safe -mtriple arm64-apple-ios -O0 -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombinerhelper-only-enable-rule="overlapping_and" -global-isel -verify-machineinstrs %s -o - | FileCheck %s
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# REQUIRES: asserts
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---
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name: bitmask_overlap1
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body: |
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bb.1:
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; CHECK-LABEL: name: bitmask_overlap1
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
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; CHECK: $w0 = COPY [[AND]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = G_CONSTANT i32 -128
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%3:_(s32) = G_CONSTANT i32 255
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%2:_(s32) = G_AND %0, %1
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%4:_(s32) = G_AND %2, %3
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$w0 = COPY %4(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: bitmask_overlap2
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body: |
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bb.1:
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; CHECK-LABEL: name: bitmask_overlap2
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
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; CHECK: $w0 = COPY [[AND]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = G_CONSTANT i32 255
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%3:_(s32) = G_CONSTANT i32 -128
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%2:_(s32) = G_AND %1, %0
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%4:_(s32) = G_AND %2, %3
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$w0 = COPY %4(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: bitmask_overlap3
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body: |
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bb.1:
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; CHECK-LABEL: name: bitmask_overlap3
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
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; CHECK: $w0 = COPY [[AND]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = G_CONSTANT i32 255
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%3:_(s32) = G_CONSTANT i32 -128
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%2:_(s32) = G_AND %1, %0
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%4:_(s32) = G_AND %3, %2
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$w0 = COPY %4(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: bitmask_overlap4
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body: |
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bb.1:
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; CHECK-LABEL: name: bitmask_overlap4
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
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; CHECK: $w0 = COPY [[AND]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = G_CONSTANT i32 255
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%3:_(s32) = G_CONSTANT i32 -128
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%2:_(s32) = G_AND %0, %1
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%4:_(s32) = G_AND %3, %2
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$w0 = COPY %4(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: bitmask_no_overlap
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body: |
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bb.1:
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; CHECK-LABEL: name: bitmask_no_overlap
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: $w0 = COPY [[C]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = G_CONSTANT i32 1
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%3:_(s32) = G_CONSTANT i32 2
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%2:_(s32) = G_AND %0, %1
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%4:_(s32) = G_AND %2, %3
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$w0 = COPY %4(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: bitmask_overlap_extrause
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body: |
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bb.1:
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; CHECK-LABEL: name: bitmask_overlap_extrause
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
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; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
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; CHECK: G_STORE [[AND]](s32), [[COPY1]](p0) :: (store 4)
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; CHECK: $w0 = COPY [[AND1]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(p0) = COPY $x1
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%2:_(s32) = G_CONSTANT i32 255
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%4:_(s32) = G_CONSTANT i32 -128
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%3:_(s32) = G_AND %0, %2
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%5:_(s32) = G_AND %3, %4
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G_STORE %3(s32), %1(p0) :: (store 4)
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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@ -1151,7 +1151,7 @@ define float @v_test_sitofp_i64_byte_to_f32(i64 %arg0) {
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; SI-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
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; SI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v3
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; SI-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
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; SI-NEXT: v_and_b32_e32 v3, s6, v1
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; SI-NEXT: v_and_b32_e32 v3, s6, v3
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; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v1
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; SI-NEXT: v_lshlrev_b32_e32 v0, 23, v0
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; SI-NEXT: s_mov_b32 s4, 0
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@ -1183,7 +1183,7 @@ define float @v_test_sitofp_i64_byte_to_f32(i64 %arg0) {
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; VI-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
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; VI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v3
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; VI-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
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; VI-NEXT: v_and_b32_e32 v3, s6, v1
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; VI-NEXT: v_and_b32_e32 v3, s6, v3
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; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v1
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; VI-NEXT: v_lshlrev_b32_e32 v0, 23, v0
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; VI-NEXT: s_mov_b32 s4, 0
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@ -1218,7 +1218,7 @@ define float @v_test_uitofp_i64_byte_to_f32(i64 %arg0) {
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; SI-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
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; SI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v3
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; SI-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
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; SI-NEXT: v_and_b32_e32 v3, s4, v1
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; SI-NEXT: v_and_b32_e32 v3, s4, v3
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; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v1
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; SI-NEXT: v_lshlrev_b32_e32 v0, 23, v0
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; SI-NEXT: s_mov_b32 s4, 0
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@ -1248,7 +1248,7 @@ define float @v_test_uitofp_i64_byte_to_f32(i64 %arg0) {
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; VI-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
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; VI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v3
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; VI-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
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; VI-NEXT: v_and_b32_e32 v3, s4, v1
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; VI-NEXT: v_and_b32_e32 v3, s4, v3
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; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v1
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; VI-NEXT: v_lshlrev_b32_e32 v0, 23, v0
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; VI-NEXT: s_mov_b32 s4, 0
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@ -547,21 +547,18 @@ define amdgpu_ps i32 @s_shl_i32_zext_i16(i16 inreg %x) {
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;
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; GFX8-LABEL: s_shl_i32_zext_i16:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_and_b32 s0, s0, 0xffff
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; GFX8-NEXT: s_and_b32 s0, s0, 0x3fff
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; GFX8-NEXT: s_lshl_b32 s0, s0, 2
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; GFX8-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: s_shl_i32_zext_i16:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_and_b32 s0, s0, 0xffff
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; GFX9-NEXT: s_and_b32 s0, s0, 0x3fff
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; GFX9-NEXT: s_lshl_b32 s0, s0, 2
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: s_shl_i32_zext_i16:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_and_b32 s0, s0, 0xffff
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; GFX10-NEXT: s_and_b32 s0, s0, 0x3fff
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; GFX10-NEXT: s_lshl_b32 s0, s0, 2
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; GFX10-NEXT: ; return to shader part epilog
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