forked from OSchip/llvm-project
Make a bunch of lowering helper functions static instead of member functions. No functional change.
llvm-svn: 163596
This commit is contained in:
Craig Topper
parent
c030bcdf62
commit
a29ed865d0
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@ -5021,7 +5021,7 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
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/// The VBROADCAST node is returned when a pattern is found,
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/// or SDValue() otherwise.
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SDValue
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X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const {
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X86TargetLowering::LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const {
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if (!Subtarget->hasAVX())
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return SDValue();
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@ -5571,8 +5571,7 @@ static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
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return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
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}
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SDValue
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X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
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static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
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assert(Op.getNumOperands() == 2);
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// 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
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@ -5581,9 +5580,9 @@ X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
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}
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// Try to lower a shuffle node into a simple blend instruction.
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static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
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const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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static SDValue
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LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
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const X86Subtarget *Subtarget, SelectionDAG &DAG) {
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SDValue V1 = SVOp->getOperand(0);
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SDValue V2 = SVOp->getOperand(1);
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DebugLoc dl = SVOp->getDebugLoc();
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@ -5653,9 +5652,9 @@ static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
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// 2. [ssse3] 1 x pshufb
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// 3. [ssse3] 2 x pshufb + 1 x por
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// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
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SDValue
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X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
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SelectionDAG &DAG) const {
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static SDValue
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LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
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SDValue V1 = SVOp->getOperand(0);
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SDValue V2 = SVOp->getOperand(1);
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@ -6028,8 +6027,8 @@ SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
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// v32i8 shuffles - Translate to VPSHUFB if possible.
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static
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SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
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SelectionDAG &DAG,
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const X86TargetLowering &TLI) {
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const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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EVT VT = SVOp->getValueType(0);
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SDValue V1 = SVOp->getOperand(0);
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SDValue V2 = SVOp->getOperand(1);
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@ -6044,7 +6043,7 @@ SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
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// (1) one of input vector is undefined or zeroinitializer.
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// The mask value 0x80 puts 0 in the corresponding slot of the vector.
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// And (2) the mask indexes don't cross the 128-bit lane.
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if (VT != MVT::v32i8 || !TLI.getSubtarget()->hasAVX2() ||
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if (VT != MVT::v32i8 || !Subtarget->hasAVX2() ||
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(!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
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return SDValue();
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@ -6885,7 +6884,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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// Handle v8i16 specifically since SSE can do byte extraction and insertion.
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if (VT == MVT::v8i16) {
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SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
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SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
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if (NewOp.getNode())
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return NewOp;
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}
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@ -6897,7 +6896,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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}
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if (VT == MVT::v32i8) {
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SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, DAG, *this);
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SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
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if (NewOp.getNode())
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return NewOp;
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}
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@ -7173,8 +7172,7 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
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return SDValue();
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}
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SDValue
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X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
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LLVMContext *Context = DAG.getContext();
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DebugLoc dl = Op.getDebugLoc();
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EVT OpVT = Op.getValueType();
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@ -7206,8 +7204,8 @@ X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
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// a simple subregister reference or explicit instructions to grab
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// upper bits of a vector.
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SDValue
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X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
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static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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if (Subtarget->hasAVX()) {
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DebugLoc dl = Op.getNode()->getDebugLoc();
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SDValue Vec = Op.getNode()->getOperand(0);
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@ -7226,8 +7224,8 @@ X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
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// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
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// simple superregister reference or explicit instructions to insert
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// the upper bits of a vector.
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SDValue
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X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
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static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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if (Subtarget->hasAVX()) {
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DebugLoc dl = Op.getNode()->getDebugLoc();
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SDValue Vec = Op.getNode()->getOperand(0);
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@ -8337,7 +8335,7 @@ SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
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return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
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}
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SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
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static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
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SDValue N0 = Op.getOperand(0);
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DebugLoc dl = Op.getDebugLoc();
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EVT VT = Op.getValueType();
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@ -9587,7 +9585,8 @@ SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
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false, false, false, 0);
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}
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SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
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static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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// X86-64 va_list is a struct { i32, i32, i8*, i8* }.
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assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
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SDValue Chain = Op.getOperand(0);
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@ -9648,8 +9647,7 @@ static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
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return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
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}
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SDValue
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X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
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static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
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DebugLoc dl = Op.getDebugLoc();
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unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
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switch (IntNo) {
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@ -10186,8 +10184,7 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
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}
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}
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SDValue
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X86TargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const {
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static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
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DebugLoc dl = Op.getDebugLoc();
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unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
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switch (IntNo) {
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@ -10287,8 +10284,7 @@ SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
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Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
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}
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SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
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SelectionDAG &DAG) const {
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static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
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return Op.getOperand(0);
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}
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@ -10511,7 +10507,7 @@ SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
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ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
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}
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SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
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static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
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EVT VT = Op.getValueType();
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EVT OpVT = VT;
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unsigned NumBits = VT.getSizeInBits();
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@ -10545,8 +10541,7 @@ SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
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return Op;
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}
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SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
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SelectionDAG &DAG) const {
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static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
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EVT VT = Op.getValueType();
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EVT OpVT = VT;
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unsigned NumBits = VT.getSizeInBits();
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@ -10571,7 +10566,7 @@ SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
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return Op;
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}
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SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
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static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
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EVT VT = Op.getValueType();
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unsigned NumBits = VT.getSizeInBits();
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DebugLoc dl = Op.getDebugLoc();
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@ -10620,21 +10615,22 @@ static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
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DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
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}
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SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
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static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
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assert(Op.getValueType().is256BitVector() &&
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Op.getValueType().isInteger() &&
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"Only handle AVX 256-bit vector integer operation");
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return Lower256IntArith(Op, DAG);
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}
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SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
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static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
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assert(Op.getValueType().is256BitVector() &&
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Op.getValueType().isInteger() &&
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"Only handle AVX 256-bit vector integer operation");
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return Lower256IntArith(Op, DAG);
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}
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SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
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static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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EVT VT = Op.getValueType();
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// Decompose 256-bit ops into smaller 128-bit ops.
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@ -10909,7 +10905,7 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
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return SDValue();
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}
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SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
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static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
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// Lower the "add/sub/mul with overflow" instruction into a regular ins plus
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// a "setcc" instruction that checks the overflow flag. The "brcond" lowering
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// looks for this combo and may remove the "setcc" instruction if the "setcc"
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@ -11037,7 +11033,8 @@ SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
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}
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SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
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static SDValue LowerMEMBARRIER(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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DebugLoc dl = Op.getDebugLoc();
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// Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
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@ -11082,8 +11079,8 @@ SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
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return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
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}
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SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
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SelectionDAG &DAG) const {
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static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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DebugLoc dl = Op.getDebugLoc();
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AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
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cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
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@ -11121,7 +11118,8 @@ SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
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}
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SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
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static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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EVT T = Op.getValueType();
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DebugLoc DL = Op.getDebugLoc();
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unsigned Reg = 0;
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@ -11152,8 +11150,8 @@ SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
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return cpOut;
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}
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SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
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SelectionDAG &DAG) const {
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static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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assert(Subtarget->is64Bit() && "Result not type legalized?");
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SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
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SDValue TheChain = Op.getOperand(0);
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@ -11171,8 +11169,7 @@ SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
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return DAG.getMergeValues(Ops, 2, dl);
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}
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SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
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SelectionDAG &DAG) const {
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SDValue X86TargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
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EVT SrcVT = Op.getOperand(0).getValueType();
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EVT DstVT = Op.getValueType();
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assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
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@ -11192,7 +11189,7 @@ SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
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return SDValue();
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}
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SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
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static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
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SDNode *Node = Op.getNode();
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DebugLoc dl = Node->getDebugLoc();
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EVT T = Node->getValueType(0);
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@ -11265,9 +11262,9 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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switch (Op.getOpcode()) {
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default: llvm_unreachable("Should not custom lower this!");
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case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
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case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
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case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
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case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
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case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, Subtarget, DAG);
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case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
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case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
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case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
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case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
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case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
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@ -11275,8 +11272,8 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
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case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
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case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
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case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
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case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
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case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
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case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
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case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
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case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
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case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
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@ -11300,7 +11297,7 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::JumpTable: return LowerJumpTable(Op, DAG);
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case ISD::VASTART: return LowerVASTART(Op, DAG);
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case ISD::VAARG: return LowerVAARG(Op, DAG);
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case ISD::VACOPY: return LowerVACOPY(Op, DAG);
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case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
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case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
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case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
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case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
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@ -11315,7 +11312,7 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::CTLZ: return LowerCTLZ(Op, DAG);
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case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
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case ISD::CTTZ: return LowerCTTZ(Op, DAG);
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case ISD::MUL: return LowerMUL(Op, DAG);
|
||||
case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
|
||||
case ISD::SRA:
|
||||
case ISD::SRL:
|
||||
case ISD::SHL: return LowerShift(Op, DAG);
|
||||
|
|
@ -11325,7 +11322,7 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
|
|||
case ISD::USUBO:
|
||||
case ISD::SMULO:
|
||||
case ISD::UMULO: return LowerXALUO(Op, DAG);
|
||||
case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
|
||||
case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
|
||||
case ISD::BITCAST: return LowerBITCAST(Op, DAG);
|
||||
case ISD::ADDC:
|
||||
case ISD::ADDE:
|
||||
|
|
@ -13498,12 +13495,12 @@ static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
|
|||
}
|
||||
|
||||
|
||||
/// DCI, PerformTruncateCombine - Converts truncate operation to
|
||||
/// PerformTruncateCombine - Converts truncate operation to
|
||||
/// a sequence of vector shuffle operations.
|
||||
/// It is possible when we truncate 256-bit vector to 128-bit vector
|
||||
|
||||
SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
|
||||
DAGCombinerInfo &DCI) const {
|
||||
static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
|
||||
TargetLowering::DAGCombinerInfo &DCI,
|
||||
const X86Subtarget *Subtarget) {
|
||||
if (!DCI.isBeforeLegalizeOps())
|
||||
return SDValue();
|
||||
|
||||
|
|
@ -16114,7 +16111,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
|
|||
case ISD::ANY_EXTEND:
|
||||
case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
|
||||
case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
|
||||
case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
|
||||
case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
|
||||
case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
|
||||
case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
|
||||
case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
|
||||
|
|
|
|||
|
|
@ -763,15 +763,11 @@ namespace llvm {
|
|||
SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
|
||||
SelectionDAG &DAG) const;
|
||||
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
|
||||
|
|
@ -790,7 +786,6 @@ namespace llvm {
|
|||
SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerToBT(SDValue And, ISD::CondCode CC,
|
||||
DebugLoc dl, SelectionDAG &DAG) const;
|
||||
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
|
||||
|
|
@ -802,36 +797,18 @@ namespace llvm {
|
|||
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
|
||||
|
||||
SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue PerformTruncateCombine(SDNode* N, SelectionDAG &DAG, DAGCombinerInfo &DCI) const;
|
||||
|
||||
// Utility functions to help LowerVECTOR_SHUFFLE
|
||||
SDValue LowerVECTOR_SHUFFLEv8i16(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const;
|
||||
|
||||
SDValue LowerVectorFpExtend(SDValue &Op, SelectionDAG &DAG) const;
|
||||
|
|
|
|||
Loading…
Reference in New Issue