forked from OSchip/llvm-project
[X86] Remove some unused masked conversion intrinsics that can be replaced with an older intrinsic and a select.
This is what clang already uses. llvm-svn: 332170
This commit is contained in:
Craig Topper
parent
107f55005b
commit
a288f241cd
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@ -3683,16 +3683,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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// Vector convert
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_avx512_mask_cvtdq2ps_128 : // TODO: remove this intrinsic
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Intrinsic<[llvm_v4f32_ty],
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[llvm_v4i32_ty, llvm_v4f32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtdq2ps_256 : // TODO: remove this intrinsic
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Intrinsic<[llvm_v8f32_ty],
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[llvm_v8i32_ty, llvm_v8f32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtdq2ps_512 :
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GCCBuiltin<"__builtin_ia32_cvtdq2ps512_mask">,
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Intrinsic<[llvm_v16f32_ty],
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@ -3705,22 +3695,12 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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[llvm_v2f64_ty, llvm_v4i32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtpd2dq_256 : // TODO: remove this intrinsic
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v4f64_ty, llvm_v4i32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtpd2dq_512 :
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GCCBuiltin<"__builtin_ia32_cvtpd2dq512_mask">,
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Intrinsic<[llvm_v8i32_ty],
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[llvm_v8f64_ty, llvm_v8i32_ty, llvm_i8_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtpd2ps_256 : // TODO: remove this intrinsic
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Intrinsic<[llvm_v4f32_ty],
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[llvm_v4f64_ty, llvm_v4f32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtpd2ps_512 :
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GCCBuiltin<"__builtin_ia32_cvtpd2ps512_mask">,
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Intrinsic<[llvm_v8f32_ty],
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@ -3817,16 +3797,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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[llvm_v16f32_ty, llvm_v16i32_ty, llvm_i16_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtps2pd_128 : // FIXME: remove this intrinsic
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Intrinsic<[llvm_v2f64_ty],
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[llvm_v4f32_ty, llvm_v2f64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtps2pd_256 : // FIXME: remove this intrinsic
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Intrinsic<[llvm_v4f64_ty],
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[llvm_v4f32_ty, llvm_v4f64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtps2pd_512 :
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GCCBuiltin<"__builtin_ia32_cvtps2pd512_mask">,
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Intrinsic<[llvm_v8f64_ty],
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@ -3929,11 +3899,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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[llvm_v2f64_ty, llvm_v4i32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvttpd2dq_256 : // TODO: remove this intrinsic
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v4f64_ty, llvm_v4i32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvttpd2dq_512 :
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GCCBuiltin<"__builtin_ia32_cvttpd2dq512_mask">,
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Intrinsic<[llvm_v8i32_ty],
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@ -3994,16 +3959,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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[llvm_v8f64_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvttps2dq_128 : // TODO: remove this intrinsic
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v4f32_ty, llvm_v4i32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvttps2dq_256 : // TODO: remove this intrinsic
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Intrinsic<[llvm_v8i32_ty],
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[llvm_v8f32_ty, llvm_v8i32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvttps2dq_512 :
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GCCBuiltin<"__builtin_ia32_cvttps2dq512_mask">,
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Intrinsic<[llvm_v16i32_ty],
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@ -172,6 +172,15 @@ static bool ShouldUpgradeX86Intrinsic(Function *F, StringRef Name) {
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Name.startswith("avx512.mask.pmull.") || // Added in 4.0
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Name.startswith("avx512.mask.cvtdq2pd.") || // Added in 4.0
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Name.startswith("avx512.mask.cvtudq2pd.") || // Added in 4.0
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Name == "avx512.mask.cvtdq2ps.128" || // Added in 7.0
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Name == "avx512.mask.cvtdq2ps.256" || // Added in 7.0
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Name == "avx512.mask.cvtpd2dq.256" || // Added in 7.0
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Name == "avx512.mask.cvtpd2ps.256" || // Added in 7.0
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Name == "avx512.mask.cvttpd2dq.256" || // Added in 7.0
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Name == "avx512.mask.cvttps2dq.128" || // Added in 7.0
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Name == "avx512.mask.cvttps2dq.256" || // Added in 7.0
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Name == "avx512.mask.cvtps2pd.128" || // Added in 7.0
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Name == "avx512.mask.cvtps2pd.256" || // Added in 7.0
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Name == "sse2.pmulu.dq" || // Added in 7.0
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Name == "sse41.pmuldq" || // Added in 7.0
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Name == "avx2.pmulu.dq" || // Added in 7.0
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@ -1175,13 +1184,32 @@ static bool upgradeAVX512MaskToSelect(StringRef Name, IRBuilder<> &Builder,
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IID = Intrinsic::x86_avx512_vpermilvar_pd_512;
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else
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llvm_unreachable("Unexpected intrinsic");
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} else if (Name == "cvtdq2ps.128") {
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IID = Intrinsic::x86_sse2_cvtdq2ps;
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} else if (Name == "cvtdq2ps.256") {
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IID = Intrinsic::x86_avx_cvtdq2_ps_256;
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} else if (Name == "cvtpd2dq.256") {
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IID = Intrinsic::x86_avx_cvt_pd2dq_256;
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} else if (Name == "cvtpd2ps.256") {
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IID = Intrinsic::x86_avx_cvt_pd2_ps_256;
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} else if (Name == "cvttpd2dq.256") {
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IID = Intrinsic::x86_avx_cvtt_pd2dq_256;
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} else if (Name == "cvttps2dq.128") {
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IID = Intrinsic::x86_sse2_cvttps2dq;
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} else if (Name == "cvttps2dq.256") {
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IID = Intrinsic::x86_avx_cvtt_ps2dq_256;
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} else
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return false;
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SmallVector<Value *, 4> Args(CI.arg_operands().begin(),
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CI.arg_operands().end());
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Args.pop_back();
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Args.pop_back();
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Rep = Builder.CreateCall(Intrinsic::getDeclaration(CI.getModule(), IID),
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{ CI.getArgOperand(0), CI.getArgOperand(1) });
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Rep = EmitX86Select(Builder, CI.getArgOperand(3), Rep,
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CI.getArgOperand(2));
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Args);
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unsigned NumArgs = CI.getNumArgOperands();
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Rep = EmitX86Select(Builder, CI.getArgOperand(NumArgs - 1), Rep,
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CI.getArgOperand(NumArgs - 2));
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return true;
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}
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@ -1524,6 +1552,8 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
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Name == "sse2.cvtps2pd" ||
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Name == "avx.cvtdq2.pd.256" ||
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Name == "avx.cvt.ps2.pd.256" ||
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Name == "avx512.mask.cvtps2pd.128" ||
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Name == "avx512.mask.cvtps2pd.256" ||
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Name.startswith("avx512.mask.cvtdq2pd.") ||
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Name.startswith("avx512.mask.cvtudq2pd."))) {
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// Lossless i32/float to double conversion.
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@ -533,22 +533,14 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86ISD::CONFLICT, 0),
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X86_INTRINSIC_DATA(avx512_mask_conflict_q_512, INTR_TYPE_1OP_MASK,
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X86ISD::CONFLICT, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtdq2ps_128, INTR_TYPE_1OP_MASK,
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ISD::SINT_TO_FP, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtdq2ps_256, INTR_TYPE_1OP_MASK,
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ISD::SINT_TO_FP, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtdq2ps_512, INTR_TYPE_1OP_MASK,
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ISD::SINT_TO_FP, X86ISD::SINT_TO_FP_RND), //er
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2dq_128, INTR_TYPE_1OP_MASK,
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X86ISD::CVTP2SI, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2dq_256, INTR_TYPE_1OP_MASK,
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X86ISD::CVTP2SI, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2dq_512, INTR_TYPE_1OP_MASK,
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X86ISD::CVTP2SI, X86ISD::CVTP2SI_RND),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2ps, INTR_TYPE_1OP_MASK,
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X86ISD::VFPROUND, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2ps_256, CVTPD2PS_MASK,
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ISD::FP_ROUND, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2ps_512, CVTPD2PS_MASK,
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ISD::FP_ROUND, X86ISD::VFPROUND_RND),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2qq_128, INTR_TYPE_1OP_MASK,
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@ -575,10 +567,6 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86ISD::CVTP2SI, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtps2dq_512, INTR_TYPE_1OP_MASK,
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X86ISD::CVTP2SI, X86ISD::CVTP2SI_RND),
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X86_INTRINSIC_DATA(avx512_mask_cvtps2pd_128, INTR_TYPE_1OP_MASK,
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X86ISD::VFPEXT, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtps2pd_256, INTR_TYPE_1OP_MASK,
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ISD::FP_EXTEND, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtps2pd_512, INTR_TYPE_1OP_MASK,
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ISD::FP_EXTEND, X86ISD::VFPEXT_RND),
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X86_INTRINSIC_DATA(avx512_mask_cvtps2qq_128, INTR_TYPE_1OP_MASK,
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@ -617,8 +605,6 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86ISD::VFPEXTS_RND, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvttpd2dq_128, INTR_TYPE_1OP_MASK,
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X86ISD::CVTTP2SI, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvttpd2dq_256, INTR_TYPE_1OP_MASK,
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ISD::FP_TO_SINT, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvttpd2dq_512, INTR_TYPE_1OP_MASK,
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ISD::FP_TO_SINT, X86ISD::CVTTP2SI_RND),
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X86_INTRINSIC_DATA(avx512_mask_cvttpd2qq_128, INTR_TYPE_1OP_MASK,
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@ -639,10 +625,6 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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ISD::FP_TO_UINT, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvttpd2uqq_512, INTR_TYPE_1OP_MASK,
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ISD::FP_TO_UINT, X86ISD::CVTTP2UI_RND),
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X86_INTRINSIC_DATA(avx512_mask_cvttps2dq_128, INTR_TYPE_1OP_MASK,
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ISD::FP_TO_SINT, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvttps2dq_256, INTR_TYPE_1OP_MASK,
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ISD::FP_TO_SINT, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvttps2dq_512, INTR_TYPE_1OP_MASK,
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ISD::FP_TO_SINT, X86ISD::CVTTP2SI_RND),
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X86_INTRINSIC_DATA(avx512_mask_cvttps2qq_128, INTR_TYPE_1OP_MASK,
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@ -6593,3 +6593,147 @@ define < 4 x i64> @test_mask_mul_epu32_rmbkz_256(< 8 x i32> %a, i64* %ptr_b, i8
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}
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declare < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32>, < 8 x i32>, < 4 x i64>, i8)
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declare <4 x float> @llvm.x86.avx512.mask.cvtdq2ps.128(<4 x i32>, <4 x float>, i8)
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define <4 x float>@test_int_x86_avx512_mask_cvt_dq2ps_128(<4 x i32> %x0, <4 x float> %x1, i8 %x2) {
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; CHECK-LABEL: test_int_x86_avx512_mask_cvt_dq2ps_128:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm2 ## EVEX TO VEX Compression encoding: [0xc5,0xf8,0x5b,0xd0]
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; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
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; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x09,0x5b,0xc8]
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; CHECK-NEXT: vaddps %xmm2, %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf0,0x58,0xc2]
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; CHECK-NEXT: retq ## encoding: [0xc3]
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%res = call <4 x float> @llvm.x86.avx512.mask.cvtdq2ps.128(<4 x i32> %x0, <4 x float> %x1, i8 %x2)
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%res1 = call <4 x float> @llvm.x86.avx512.mask.cvtdq2ps.128(<4 x i32> %x0, <4 x float> %x1, i8 -1)
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%res2 = fadd <4 x float> %res, %res1
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ret <4 x float> %res2
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}
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declare <8 x float> @llvm.x86.avx512.mask.cvtdq2ps.256(<8 x i32>, <8 x float>, i8)
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define <8 x float>@test_int_x86_avx512_mask_cvt_dq2ps_256(<8 x i32> %x0, <8 x float> %x1, i8 %x2) {
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; CHECK-LABEL: test_int_x86_avx512_mask_cvt_dq2ps_256:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vcvtdq2ps %ymm0, %ymm2 ## EVEX TO VEX Compression encoding: [0xc5,0xfc,0x5b,0xd0]
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; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
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; CHECK-NEXT: vcvtdq2ps %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x29,0x5b,0xc8]
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; CHECK-NEXT: vaddps %ymm2, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf4,0x58,0xc2]
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; CHECK-NEXT: retq ## encoding: [0xc3]
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%res = call <8 x float> @llvm.x86.avx512.mask.cvtdq2ps.256(<8 x i32> %x0, <8 x float> %x1, i8 %x2)
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%res1 = call <8 x float> @llvm.x86.avx512.mask.cvtdq2ps.256(<8 x i32> %x0, <8 x float> %x1, i8 -1)
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%res2 = fadd <8 x float> %res, %res1
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ret <8 x float> %res2
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}
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declare <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.256(<4 x double>, <4 x i32>, i8)
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define <4 x i32>@test_int_x86_avx512_mask_cvt_pd2dq_256(<4 x double> %x0, <4 x i32> %x1, i8 %x2) {
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; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2dq_256:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vcvtpd2dq %ymm0, %xmm2 ## EVEX TO VEX Compression encoding: [0xc5,0xff,0xe6,0xd0]
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; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
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; CHECK-NEXT: vcvtpd2dq %ymm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0xff,0x29,0xe6,0xc8]
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; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf1,0xfe,0xc2]
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; CHECK-NEXT: retq ## encoding: [0xc3]
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%res = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.256(<4 x double> %x0, <4 x i32> %x1, i8 %x2)
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%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.256(<4 x double> %x0, <4 x i32> %x1, i8 -1)
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%res2 = add <4 x i32> %res, %res1
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ret <4 x i32> %res2
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}
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declare <4 x float> @llvm.x86.avx512.mask.cvtpd2ps.256(<4 x double>, <4 x float>, i8)
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define <4 x float>@test_int_x86_avx512_mask_cvt_pd2ps_256(<4 x double> %x0, <4 x float> %x1, i8 %x2) {
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; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2ps_256:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vcvtpd2ps %ymm0, %xmm2 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x5a,0xd0]
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; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
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; CHECK-NEXT: vcvtpd2ps %ymm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x29,0x5a,0xc8]
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; CHECK-NEXT: vaddps %xmm2, %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf0,0x58,0xc2]
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; CHECK-NEXT: retq ## encoding: [0xc3]
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%res = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps.256(<4 x double> %x0, <4 x float> %x1, i8 %x2)
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%res1 = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps.256(<4 x double> %x0, <4 x float> %x1, i8 -1)
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%res2 = fadd <4 x float> %res, %res1
|
||||
ret <4 x float> %res2
|
||||
}
|
||||
|
||||
declare <4 x double> @llvm.x86.avx512.mask.cvtps2pd.256(<4 x float>, <4 x double>, i8)
|
||||
|
||||
define <4 x double>@test_int_x86_avx512_mask_cvt_ps2pd_256(<4 x float> %x0, <4 x double> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2pd_256:
|
||||
; CHECK: ## %bb.0:
|
||||
; CHECK-NEXT: vcvtps2pd %xmm0, %ymm2 ## EVEX TO VEX Compression encoding: [0xc5,0xfc,0x5a,0xd0]
|
||||
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
|
||||
; CHECK-NEXT: vcvtps2pd %xmm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x29,0x5a,0xc8]
|
||||
; CHECK-NEXT: vaddpd %ymm2, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf5,0x58,0xc2]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
%res = call <4 x double> @llvm.x86.avx512.mask.cvtps2pd.256(<4 x float> %x0, <4 x double> %x1, i8 %x2)
|
||||
%res1 = call <4 x double> @llvm.x86.avx512.mask.cvtps2pd.256(<4 x float> %x0, <4 x double> %x1, i8 -1)
|
||||
%res2 = fadd <4 x double> %res, %res1
|
||||
ret <4 x double> %res2
|
||||
}
|
||||
|
||||
declare <2 x double> @llvm.x86.avx512.mask.cvtps2pd.128(<4 x float>, <2 x double>, i8)
|
||||
|
||||
define <2 x double>@test_int_x86_avx512_mask_cvt_ps2pd_128(<4 x float> %x0, <2 x double> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2pd_128:
|
||||
; CHECK: ## %bb.0:
|
||||
; CHECK-NEXT: vcvtps2pd %xmm0, %xmm2 ## EVEX TO VEX Compression encoding: [0xc5,0xf8,0x5a,0xd0]
|
||||
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
|
||||
; CHECK-NEXT: vcvtps2pd %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x09,0x5a,0xc8]
|
||||
; CHECK-NEXT: vaddpd %xmm2, %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf1,0x58,0xc2]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
%res = call <2 x double> @llvm.x86.avx512.mask.cvtps2pd.128(<4 x float> %x0, <2 x double> %x1, i8 %x2)
|
||||
%res1 = call <2 x double> @llvm.x86.avx512.mask.cvtps2pd.128(<4 x float> %x0, <2 x double> %x1, i8 -1)
|
||||
%res2 = fadd <2 x double> %res, %res1
|
||||
ret <2 x double> %res2
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.256(<4 x double>, <4 x i32>, i8)
|
||||
|
||||
define <4 x i32>@test_int_x86_avx512_mask_cvtt_pd2dq_256(<4 x double> %x0, <4 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2dq_256:
|
||||
; CHECK: ## %bb.0:
|
||||
; CHECK-NEXT: vcvttpd2dq %ymm0, %xmm2 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe6,0xd0]
|
||||
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
|
||||
; CHECK-NEXT: vcvttpd2dq %ymm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x29,0xe6,0xc8]
|
||||
; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf1,0xfe,0xc2]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
%res = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.256(<4 x double> %x0, <4 x i32> %x1, i8 %x2)
|
||||
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.256(<4 x double> %x0, <4 x i32> %x1, i8 -1)
|
||||
%res2 = add <4 x i32> %res, %res1
|
||||
ret <4 x i32> %res2
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.cvttps2dq.128(<4 x float>, <4 x i32>, i8)
|
||||
|
||||
define <4 x i32>@test_int_x86_avx512_mask_cvtt_ps2dq_128(<4 x float> %x0, <4 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2dq_128:
|
||||
; CHECK: ## %bb.0:
|
||||
; CHECK-NEXT: vcvttps2dq %xmm0, %xmm2 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x5b,0xd0]
|
||||
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
|
||||
; CHECK-NEXT: vcvttps2dq %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7e,0x09,0x5b,0xc8]
|
||||
; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf1,0xfe,0xc2]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
%res = call <4 x i32> @llvm.x86.avx512.mask.cvttps2dq.128(<4 x float> %x0, <4 x i32> %x1, i8 %x2)
|
||||
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvttps2dq.128(<4 x float> %x0, <4 x i32> %x1, i8 -1)
|
||||
%res2 = add <4 x i32> %res, %res1
|
||||
ret <4 x i32> %res2
|
||||
}
|
||||
|
||||
declare <8 x i32> @llvm.x86.avx512.mask.cvttps2dq.256(<8 x float>, <8 x i32>, i8)
|
||||
|
||||
define <8 x i32>@test_int_x86_avx512_mask_cvtt_ps2dq_256(<8 x float> %x0, <8 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2dq_256:
|
||||
; CHECK: ## %bb.0:
|
||||
; CHECK-NEXT: vcvttps2dq %ymm0, %ymm2 ## EVEX TO VEX Compression encoding: [0xc5,0xfe,0x5b,0xd0]
|
||||
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
|
||||
; CHECK-NEXT: vcvttps2dq %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7e,0x29,0x5b,0xc8]
|
||||
; CHECK-NEXT: vpaddd %ymm2, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf5,0xfe,0xc2]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
%res = call <8 x i32> @llvm.x86.avx512.mask.cvttps2dq.256(<8 x float> %x0, <8 x i32> %x1, i8 %x2)
|
||||
%res1 = call <8 x i32> @llvm.x86.avx512.mask.cvttps2dq.256(<8 x float> %x0, <8 x i32> %x1, i8 -1)
|
||||
%res2 = add <8 x i32> %res, %res1
|
||||
ret <8 x i32> %res2
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1760,38 +1760,6 @@ define void @test_int_x86_avx512_mask_pmovus_dw_mem_256(i8* %ptr, <8 x i32> %x1,
|
|||
ret void
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.x86.avx512.mask.cvtdq2ps.128(<4 x i32>, <4 x float>, i8)
|
||||
|
||||
define <4 x float>@test_int_x86_avx512_mask_cvt_dq2ps_128(<4 x i32> %x0, <4 x float> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_dq2ps_128:
|
||||
; CHECK: ## %bb.0:
|
||||
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
|
||||
; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x09,0x5b,0xc8]
|
||||
; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf8,0x5b,0xc0]
|
||||
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf0,0x58,0xc0]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
%res = call <4 x float> @llvm.x86.avx512.mask.cvtdq2ps.128(<4 x i32> %x0, <4 x float> %x1, i8 %x2)
|
||||
%res1 = call <4 x float> @llvm.x86.avx512.mask.cvtdq2ps.128(<4 x i32> %x0, <4 x float> %x1, i8 -1)
|
||||
%res2 = fadd <4 x float> %res, %res1
|
||||
ret <4 x float> %res2
|
||||
}
|
||||
|
||||
declare <8 x float> @llvm.x86.avx512.mask.cvtdq2ps.256(<8 x i32>, <8 x float>, i8)
|
||||
|
||||
define <8 x float>@test_int_x86_avx512_mask_cvt_dq2ps_256(<8 x i32> %x0, <8 x float> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_dq2ps_256:
|
||||
; CHECK: ## %bb.0:
|
||||
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
|
||||
; CHECK-NEXT: vcvtdq2ps %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x29,0x5b,0xc8]
|
||||
; CHECK-NEXT: vcvtdq2ps %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfc,0x5b,0xc0]
|
||||
; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf4,0x58,0xc0]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
%res = call <8 x float> @llvm.x86.avx512.mask.cvtdq2ps.256(<8 x i32> %x0, <8 x float> %x1, i8 %x2)
|
||||
%res1 = call <8 x float> @llvm.x86.avx512.mask.cvtdq2ps.256(<8 x i32> %x0, <8 x float> %x1, i8 -1)
|
||||
%res2 = fadd <8 x float> %res, %res1
|
||||
ret <8 x float> %res2
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.128(<2 x double>, <4 x i32>, i8)
|
||||
|
||||
define <4 x i32>@test_int_x86_avx512_mask_cvt_pd2dq_128(<2 x double> %x0, <4 x i32> %x1, i8 %x2) {
|
||||
|
|
@ -1826,38 +1794,6 @@ define <4 x i32>@test_int_x86_avx512_mask_cvt_pd2dq_128_zext(<2 x double> %x0, <
|
|||
ret <4 x i32> %res4
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.256(<4 x double>, <4 x i32>, i8)
|
||||
|
||||
define <4 x i32>@test_int_x86_avx512_mask_cvt_pd2dq_256(<4 x double> %x0, <4 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2dq_256:
|
||||
; CHECK: ## %bb.0:
|
||||
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
|
||||
; CHECK-NEXT: vcvtpd2dq %ymm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0xff,0x29,0xe6,0xc8]
|
||||
; CHECK-NEXT: vcvtpd2dq %ymm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xff,0xe6,0xc0]
|
||||
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf1,0xfe,0xc0]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
%res = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.256(<4 x double> %x0, <4 x i32> %x1, i8 %x2)
|
||||
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.256(<4 x double> %x0, <4 x i32> %x1, i8 -1)
|
||||
%res2 = add <4 x i32> %res, %res1
|
||||
ret <4 x i32> %res2
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.x86.avx512.mask.cvtpd2ps.256(<4 x double>, <4 x float>, i8)
|
||||
|
||||
define <4 x float>@test_int_x86_avx512_mask_cvt_pd2ps_256(<4 x double> %x0, <4 x float> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2ps_256:
|
||||
; CHECK: ## %bb.0:
|
||||
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
|
||||
; CHECK-NEXT: vcvtpd2ps %ymm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x29,0x5a,0xc8]
|
||||
; CHECK-NEXT: vcvtpd2ps %ymm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x5a,0xc0]
|
||||
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf0,0x58,0xc0]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
%res = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps.256(<4 x double> %x0, <4 x float> %x1, i8 %x2)
|
||||
%res1 = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps.256(<4 x double> %x0, <4 x float> %x1, i8 -1)
|
||||
%res2 = fadd <4 x float> %res, %res1
|
||||
ret <4 x float> %res2
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.x86.avx512.mask.cvtpd2ps(<2 x double>, <4 x float>, i8)
|
||||
|
||||
define <4 x float>@test_int_x86_avx512_mask_cvt_pd2ps(<2 x double> %x0, <4 x float> %x1, i8 %x2) {
|
||||
|
|
@ -1974,38 +1910,6 @@ define <8 x i32>@test_int_x86_avx512_mask_cvt_ps2dq_256(<8 x float> %x0, <8 x i3
|
|||
ret <8 x i32> %res2
|
||||
}
|
||||
|
||||
declare <2 x double> @llvm.x86.avx512.mask.cvtps2pd.128(<4 x float>, <2 x double>, i8)
|
||||
|
||||
define <2 x double>@test_int_x86_avx512_mask_cvt_ps2pd_128(<4 x float> %x0, <2 x double> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2pd_128:
|
||||
; CHECK: ## %bb.0:
|
||||
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
|
||||
; CHECK-NEXT: vcvtps2pd %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x09,0x5a,0xc8]
|
||||
; CHECK-NEXT: vcvtps2pd %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf8,0x5a,0xc0]
|
||||
; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf1,0x58,0xc0]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
%res = call <2 x double> @llvm.x86.avx512.mask.cvtps2pd.128(<4 x float> %x0, <2 x double> %x1, i8 %x2)
|
||||
%res1 = call <2 x double> @llvm.x86.avx512.mask.cvtps2pd.128(<4 x float> %x0, <2 x double> %x1, i8 -1)
|
||||
%res2 = fadd <2 x double> %res, %res1
|
||||
ret <2 x double> %res2
|
||||
}
|
||||
|
||||
declare <4 x double> @llvm.x86.avx512.mask.cvtps2pd.256(<4 x float>, <4 x double>, i8)
|
||||
|
||||
define <4 x double>@test_int_x86_avx512_mask_cvt_ps2pd_256(<4 x float> %x0, <4 x double> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2pd_256:
|
||||
; CHECK: ## %bb.0:
|
||||
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
|
||||
; CHECK-NEXT: vcvtps2pd %xmm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x29,0x5a,0xc8]
|
||||
; CHECK-NEXT: vcvtps2pd %xmm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfc,0x5a,0xc0]
|
||||
; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf5,0x58,0xc0]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
%res = call <4 x double> @llvm.x86.avx512.mask.cvtps2pd.256(<4 x float> %x0, <4 x double> %x1, i8 %x2)
|
||||
%res1 = call <4 x double> @llvm.x86.avx512.mask.cvtps2pd.256(<4 x float> %x0, <4 x double> %x1, i8 -1)
|
||||
%res2 = fadd <4 x double> %res, %res1
|
||||
ret <4 x double> %res2
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.cvtps2udq.128(<4 x float>, <4 x i32>, i8)
|
||||
|
||||
define <4 x i32>@test_int_x86_avx512_mask_cvt_ps2udq_128(<4 x float> %x0, <4 x i32> %x1, i8 %x2) {
|
||||
|
|
@ -2072,22 +1976,6 @@ define <4 x i32>@test_int_x86_avx512_mask_cvtt_pd2dq_128_zext(<2 x double> %x0,
|
|||
ret <4 x i32> %res4
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.256(<4 x double>, <4 x i32>, i8)
|
||||
|
||||
define <4 x i32>@test_int_x86_avx512_mask_cvtt_pd2dq_256(<4 x double> %x0, <4 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2dq_256:
|
||||
; CHECK: ## %bb.0:
|
||||
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
|
||||
; CHECK-NEXT: vcvttpd2dq %ymm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x29,0xe6,0xc8]
|
||||
; CHECK-NEXT: vcvttpd2dq %ymm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe6,0xc0]
|
||||
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf1,0xfe,0xc0]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
%res = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.256(<4 x double> %x0, <4 x i32> %x1, i8 %x2)
|
||||
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.256(<4 x double> %x0, <4 x i32> %x1, i8 -1)
|
||||
%res2 = add <4 x i32> %res, %res1
|
||||
ret <4 x i32> %res2
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.128(<2 x double>, <4 x i32>, i8)
|
||||
|
||||
define <4 x i32>@test_int_x86_avx512_mask_cvtt_pd2udq_128(<2 x double> %x0, <4 x i32> %x1, i8 %x2) {
|
||||
|
|
@ -2138,38 +2026,6 @@ define <4 x i32>@test_int_x86_avx512_mask_cvtt_pd2udq_256(<4 x double> %x0, <4 x
|
|||
ret <4 x i32> %res2
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.cvttps2dq.128(<4 x float>, <4 x i32>, i8)
|
||||
|
||||
define <4 x i32>@test_int_x86_avx512_mask_cvtt_ps2dq_128(<4 x float> %x0, <4 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2dq_128:
|
||||
; CHECK: ## %bb.0:
|
||||
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
|
||||
; CHECK-NEXT: vcvttps2dq %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7e,0x09,0x5b,0xc8]
|
||||
; CHECK-NEXT: vcvttps2dq %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x5b,0xc0]
|
||||
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf1,0xfe,0xc0]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
%res = call <4 x i32> @llvm.x86.avx512.mask.cvttps2dq.128(<4 x float> %x0, <4 x i32> %x1, i8 %x2)
|
||||
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvttps2dq.128(<4 x float> %x0, <4 x i32> %x1, i8 -1)
|
||||
%res2 = add <4 x i32> %res, %res1
|
||||
ret <4 x i32> %res2
|
||||
}
|
||||
|
||||
declare <8 x i32> @llvm.x86.avx512.mask.cvttps2dq.256(<8 x float>, <8 x i32>, i8)
|
||||
|
||||
define <8 x i32>@test_int_x86_avx512_mask_cvtt_ps2dq_256(<8 x float> %x0, <8 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2dq_256:
|
||||
; CHECK: ## %bb.0:
|
||||
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
|
||||
; CHECK-NEXT: vcvttps2dq %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7e,0x29,0x5b,0xc8]
|
||||
; CHECK-NEXT: vcvttps2dq %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfe,0x5b,0xc0]
|
||||
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf5,0xfe,0xc0]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
%res = call <8 x i32> @llvm.x86.avx512.mask.cvttps2dq.256(<8 x float> %x0, <8 x i32> %x1, i8 %x2)
|
||||
%res1 = call <8 x i32> @llvm.x86.avx512.mask.cvttps2dq.256(<8 x float> %x0, <8 x i32> %x1, i8 -1)
|
||||
%res2 = add <8 x i32> %res, %res1
|
||||
ret <8 x i32> %res2
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.cvttps2udq.128(<4 x float>, <4 x i32>, i8)
|
||||
|
||||
define <4 x i32>@test_int_x86_avx512_mask_cvtt_ps2udq_128(<4 x float> %x0, <4 x i32> %x1, i8 %x2) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue