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[ARM][SchedModels] Move IsLDMBaseRegInListPred to ARMSchedule.td. NFC 

This predicate is not specific to cortex-a57 and can be used in other processor
models as well.
This commit is contained in:
Evgeny Leviant 2020-10-26 22:31:41 +03:00
parent 1e076a8d80
commit a28388f95b
2 changed files with 4 additions and 3 deletions
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4
llvm/lib/Target/ARM/ARMSchedule.td
View File

@ -185,6 +185,10 @@ def IsLDMBaseRegInList : CheckFunctionPredicate<
let FunctionMapper = "ARM_AM::getAM3Op" in {
class CheckAM3OpSub<int n> : CheckImmOperand_s<n, "ARM_AM::sub"> {}
}
// LDM, base reg in list
def IsLDMBaseRegInListPred : MCSchedPredicate<IsLDMBaseRegInList>;
//===----------------------------------------------------------------------===//
// Instruction Itinerary classes used for ARM
//

3
llvm/lib/Target/ARM/ARMScheduleA57.td
View File

@ -63,9 +63,6 @@ def IsLdstsoMinusRegPredX0 : MCSchedPredicate<CheckAM2OpSub<2>>;
def IsLdstsoMinusRegPred : MCSchedPredicate<CheckAM2OpSub<3>>;
def IsLdstsoMinusRegPredX2 : MCSchedPredicate<CheckAM2OpSub<4>>;
// LDM, base reg in list
def IsLDMBaseRegInListPred : MCSchedPredicate<IsLDMBaseRegInList>;
class A57WriteLMOpsListType<list<SchedWriteRes> writes> {
list <SchedWriteRes> Writes = writes;
SchedMachineModel SchedModel = ?;