From a2651266c5eb08f9dcb059247a35b1ce88ad148e Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 8 Mar 2021 09:00:17 -0800 Subject: [PATCH] [RISCV] Add explicit i64 types to RV64 isel patterns to stop tablegen from generating unneeded i32 patterns for RV32 HwMode. --- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 19 +++++++++++-------- llvm/lib/Target/RISCV/RISCVInstrInfoA.td | 14 ++++++++------ llvm/lib/Target/RISCV/RISCVInstrInfoM.td | 6 +++--- 3 files changed, 22 insertions(+), 17 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index b2f5fb3a773c..ae9167098a13 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -27,6 +27,9 @@ def SDT_RISCVSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>, SDTCisSameAs<4, 5>]>; def SDT_RISCVReadCycleWide : SDTypeProfile<2, 0, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; +def SDT_RISCVIntBinOpW : SDTypeProfile<1, 2, [ + SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<0, i64> +]>; // Target-independent nodes, but with target-specific formats. def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart, @@ -50,9 +53,9 @@ def riscv_selectcc : SDNode<"RISCVISD::SELECT_CC", SDT_RISCVSelectCC>; def riscv_tail : SDNode<"RISCVISD::TAIL", SDT_RISCVCall, [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; -def riscv_sllw : SDNode<"RISCVISD::SLLW", SDTIntShiftOp>; -def riscv_sraw : SDNode<"RISCVISD::SRAW", SDTIntShiftOp>; -def riscv_srlw : SDNode<"RISCVISD::SRLW", SDTIntShiftOp>; +def riscv_sllw : SDNode<"RISCVISD::SLLW", SDT_RISCVIntBinOpW>; +def riscv_sraw : SDNode<"RISCVISD::SRAW", SDT_RISCVIntBinOpW>; +def riscv_srlw : SDNode<"RISCVISD::SRLW", SDT_RISCVIntBinOpW>; def riscv_read_cycle_wide : SDNode<"RISCVISD::READ_CYCLE_WIDE", SDT_RISCVReadCycleWide, @@ -1131,7 +1134,7 @@ defm : LdPat; multiclass StPat { def : Pat<(StoreOp (vt StTy:$rs2), BaseAddr:$rs1), - (Inst StTy:$rs2, BaseAddr:$rs1, 0)>; + (Inst StTy:$rs2, BaseAddr:$rs1, 0)>; def : Pat<(StoreOp (vt StTy:$rs2), (add BaseAddr:$rs1, simm12:$imm12)), (Inst StTy:$rs2, BaseAddr:$rs1, simm12:$imm12)>; def : Pat<(StoreOp (vt StTy:$rs2), (IsOrAdd AddrFI:$rs1, simm12:$imm12)), @@ -1202,13 +1205,13 @@ def : Pat<(sext_inreg (sub GPR:$rs1, GPR:$rs2), i32), (SUBW GPR:$rs1, GPR:$rs2)>; def : Pat<(sext_inreg (shl GPR:$rs1, uimm5:$shamt), i32), (SLLIW GPR:$rs1, uimm5:$shamt)>; -def : Pat<(SRLIWPat GPR:$rs1, uimm5:$shamt), +def : Pat<(i64 (SRLIWPat GPR:$rs1, uimm5:$shamt)), (SRLIW GPR:$rs1, uimm5:$shamt)>; -def : Pat<(srl (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt), +def : Pat<(i64 (srl (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt)), (SRLIW GPR:$rs1, (ImmSub32 uimm6gt32:$shamt))>; def : Pat<(sra (sext_inreg GPR:$rs1, i32), uimm5:$shamt), (SRAIW GPR:$rs1, uimm5:$shamt)>; -def : Pat<(sra (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt), +def : Pat<(i64 (sra (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt)), (SRAIW GPR:$rs1, (ImmSub32 uimm6gt32:$shamt))>; def : PatGprGpr, SLLW>; @@ -1231,7 +1234,7 @@ defm : StPat; /// readcyclecounter // On RV64, we can directly read the 64-bit "cycle" CSR. let Predicates = [IsRV64] in -def : Pat<(readcyclecounter), (CSRRS CYCLE.Encoding, X0)>; +def : Pat<(i64 (readcyclecounter)), (CSRRS CYCLE.Encoding, X0)>; // On RV32, ReadCycleWide will be expanded to the suggested loop reading both // halves of the 64-bit "cycle" CSR. let Predicates = [IsRV32], usesCustomInserter = 1, hasNoSchedulingInfo = 1 in diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td index 24bc59f32726..787092b7206c 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td @@ -61,11 +61,13 @@ multiclass AMO_rr_aq_rl funct5, bits<3> funct3, string opcodestr> { def _AQ_RL : AMO_rr; } -multiclass AtomicStPat { - def : Pat<(StoreOp BaseAddr:$rs1, StTy:$rs2), (Inst StTy:$rs2, BaseAddr:$rs1, 0)>; - def : Pat<(StoreOp (add BaseAddr:$rs1, simm12:$imm12), StTy:$rs2), +multiclass AtomicStPat { + def : Pat<(StoreOp BaseAddr:$rs1, (vt StTy:$rs2)), + (Inst StTy:$rs2, BaseAddr:$rs1, 0)>; + def : Pat<(StoreOp (add BaseAddr:$rs1, simm12:$imm12), (vt StTy:$rs2)), (Inst StTy:$rs2, BaseAddr:$rs1, simm12:$imm12)>; - def : Pat<(StoreOp (IsOrAdd AddrFI:$rs1, simm12:$imm12), StTy:$rs2), + def : Pat<(StoreOp (IsOrAdd AddrFI:$rs1, simm12:$imm12), (vt StTy:$rs2)), (Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>; } @@ -317,8 +319,8 @@ let Predicates = [HasStdExtA, IsRV64] in { // Fences will be inserted for atomic load/stores according to the logic in // RISCVTargetLowering::{emitLeadingFence,emitTrailingFence}. -defm : LdPat; -defm : AtomicStPat; +defm : LdPat; +defm : AtomicStPat; defm : AMOPat<"atomic_swap_64", "AMOSWAP_D">; defm : AMOPat<"atomic_load_add_64", "AMOADD_D">; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoM.td b/llvm/lib/Target/RISCV/RISCVInstrInfoM.td index 4b92960ad013..2bfdc9312ebb 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoM.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoM.td @@ -15,9 +15,9 @@ // RISC-V specific DAG Nodes. //===----------------------------------------------------------------------===// -def riscv_divw : SDNode<"RISCVISD::DIVW", SDTIntBinOp>; -def riscv_divuw : SDNode<"RISCVISD::DIVUW", SDTIntBinOp>; -def riscv_remuw : SDNode<"RISCVISD::REMUW", SDTIntBinOp>; +def riscv_divw : SDNode<"RISCVISD::DIVW", SDT_RISCVIntBinOpW>; +def riscv_divuw : SDNode<"RISCVISD::DIVUW", SDT_RISCVIntBinOpW>; +def riscv_remuw : SDNode<"RISCVISD::REMUW", SDT_RISCVIntBinOpW>; //===----------------------------------------------------------------------===// // Instructions