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[RISCV] Add explicit i64 types to RV64 isel patterns to stop tablegen from generating unneeded i32 patterns for RV32 HwMode.

This commit is contained in:
Craig Topper 2021-03-08 09:00:17 -08:00
parent e68fafa49f
commit a2651266c5
3 changed files with 22 additions and 17 deletions
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19
llvm/lib/Target/RISCV/RISCVInstrInfo.td
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@ -27,6 +27,9 @@ def SDT_RISCVSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>,
SDTCisSameAs<4, 5>]>;
def SDT_RISCVReadCycleWide : SDTypeProfile<2, 0, [SDTCisVT<0, i32>,
SDTCisVT<1, i32>]>;
def SDT_RISCVIntBinOpW : SDTypeProfile<1, 2, [
SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<0, i64>
]>;
// Target-independent nodes, but with target-specific formats.
def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart,
@ -50,9 +53,9 @@ def riscv_selectcc : SDNode<"RISCVISD::SELECT_CC", SDT_RISCVSelectCC>;
def riscv_tail : SDNode<"RISCVISD::TAIL", SDT_RISCVCall,
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
SDNPVariadic]>;
def riscv_sllw : SDNode<"RISCVISD::SLLW", SDTIntShiftOp>;
def riscv_sraw : SDNode<"RISCVISD::SRAW", SDTIntShiftOp>;
def riscv_srlw : SDNode<"RISCVISD::SRLW", SDTIntShiftOp>;
def riscv_sllw : SDNode<"RISCVISD::SLLW", SDT_RISCVIntBinOpW>;
def riscv_sraw : SDNode<"RISCVISD::SRAW", SDT_RISCVIntBinOpW>;
def riscv_srlw : SDNode<"RISCVISD::SRLW", SDT_RISCVIntBinOpW>;
def riscv_read_cycle_wide : SDNode<"RISCVISD::READ_CYCLE_WIDE",
SDT_RISCVReadCycleWide,
@ -1131,7 +1134,7 @@ defm : LdPat<zextloadi16, LHU>;
multiclass StPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy,
ValueType vt> {
def : Pat<(StoreOp (vt StTy:$rs2), BaseAddr:$rs1),
(Inst StTy:$rs2, BaseAddr:$rs1, 0)>;
(Inst StTy:$rs2, BaseAddr:$rs1, 0)>;
def : Pat<(StoreOp (vt StTy:$rs2), (add BaseAddr:$rs1, simm12:$imm12)),
(Inst StTy:$rs2, BaseAddr:$rs1, simm12:$imm12)>;
def : Pat<(StoreOp (vt StTy:$rs2), (IsOrAdd AddrFI:$rs1, simm12:$imm12)),
@ -1202,13 +1205,13 @@ def : Pat<(sext_inreg (sub GPR:$rs1, GPR:$rs2), i32),
(SUBW GPR:$rs1, GPR:$rs2)>;
def : Pat<(sext_inreg (shl GPR:$rs1, uimm5:$shamt), i32),
(SLLIW GPR:$rs1, uimm5:$shamt)>;
def : Pat<(SRLIWPat GPR:$rs1, uimm5:$shamt),
def : Pat<(i64 (SRLIWPat GPR:$rs1, uimm5:$shamt)),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
def : Pat<(srl (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt),
def : Pat<(i64 (srl (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt)),
(SRLIW GPR:$rs1, (ImmSub32 uimm6gt32:$shamt))>;
def : Pat<(sra (sext_inreg GPR:$rs1, i32), uimm5:$shamt),
(SRAIW GPR:$rs1, uimm5:$shamt)>;
def : Pat<(sra (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt),
def : Pat<(i64 (sra (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt)),
(SRAIW GPR:$rs1, (ImmSub32 uimm6gt32:$shamt))>;
def : PatGprGpr<shiftopw<riscv_sllw>, SLLW>;
@ -1231,7 +1234,7 @@ defm : StPat<store, SD, GPR, i64>;
/// readcyclecounter
// On RV64, we can directly read the 64-bit "cycle" CSR.
let Predicates = [IsRV64] in
def : Pat<(readcyclecounter), (CSRRS CYCLE.Encoding, X0)>;
def : Pat<(i64 (readcyclecounter)), (CSRRS CYCLE.Encoding, X0)>;
// On RV32, ReadCycleWide will be expanded to the suggested loop reading both
// halves of the 64-bit "cycle" CSR.
let Predicates = [IsRV32], usesCustomInserter = 1, hasNoSchedulingInfo = 1 in

14
llvm/lib/Target/RISCV/RISCVInstrInfoA.td
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@ -61,11 +61,13 @@ multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> {
def _AQ_RL : AMO_rr<funct5, 1, 1, funct3, opcodestr # ".aqrl">;
}
multiclass AtomicStPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy> {
def : Pat<(StoreOp BaseAddr:$rs1, StTy:$rs2), (Inst StTy:$rs2, BaseAddr:$rs1, 0)>;
def : Pat<(StoreOp (add BaseAddr:$rs1, simm12:$imm12), StTy:$rs2),
multiclass AtomicStPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy,
ValueType vt = XLenVT> {
def : Pat<(StoreOp BaseAddr:$rs1, (vt StTy:$rs2)),
(Inst StTy:$rs2, BaseAddr:$rs1, 0)>;
def : Pat<(StoreOp (add BaseAddr:$rs1, simm12:$imm12), (vt StTy:$rs2)),
(Inst StTy:$rs2, BaseAddr:$rs1, simm12:$imm12)>;
def : Pat<(StoreOp (IsOrAdd AddrFI:$rs1, simm12:$imm12), StTy:$rs2),
def : Pat<(StoreOp (IsOrAdd AddrFI:$rs1, simm12:$imm12), (vt StTy:$rs2)),
(Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>;
}
@ -317,8 +319,8 @@ let Predicates = [HasStdExtA, IsRV64] in {
// Fences will be inserted for atomic load/stores according to the logic in
// RISCVTargetLowering::{emitLeadingFence,emitTrailingFence}.
defm : LdPat<atomic_load_64, LD>;
defm : AtomicStPat<atomic_store_64, SD, GPR>;
defm : LdPat<atomic_load_64, LD, i64>;
defm : AtomicStPat<atomic_store_64, SD, GPR, i64>;
defm : AMOPat<"atomic_swap_64", "AMOSWAP_D">;
defm : AMOPat<"atomic_load_add_64", "AMOADD_D">;

6
llvm/lib/Target/RISCV/RISCVInstrInfoM.td
View File

@ -15,9 +15,9 @@
// RISC-V specific DAG Nodes.
//===----------------------------------------------------------------------===//
def riscv_divw : SDNode<"RISCVISD::DIVW", SDTIntBinOp>;
def riscv_divuw : SDNode<"RISCVISD::DIVUW", SDTIntBinOp>;
def riscv_remuw : SDNode<"RISCVISD::REMUW", SDTIntBinOp>;
def riscv_divw : SDNode<"RISCVISD::DIVW", SDT_RISCVIntBinOpW>;
def riscv_divuw : SDNode<"RISCVISD::DIVUW", SDT_RISCVIntBinOpW>;
def riscv_remuw : SDNode<"RISCVISD::REMUW", SDT_RISCVIntBinOpW>;
//===----------------------------------------------------------------------===//
// Instructions