forked from OSchip/llvm-project
Propagate MIFlags in table gen
Summary: Add flag propagation to tablegen via OutMIs from originating MI in InstructionSelector::executeMatchTable. Reviewers: dsanders, volkan Reviewed By: dsanders Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74988
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@ -57,6 +57,7 @@ bool InstructionSelector::executeMatchTable(
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uint64_t CurrentIdx = 0;
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SmallVector<uint64_t, 4> OnFailResumeAt;
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uint16_t Flags = State.MIs[0]->getFlags();
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enum RejectAction { RejectAndGiveUp, RejectAndResume };
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auto handleReject = [&]() -> RejectAction {
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@ -71,6 +72,15 @@ bool InstructionSelector::executeMatchTable(
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return RejectAndResume;
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};
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auto propagateFlags = [&](NewMIVector &OutMIs) {
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if (Flags == MachineInstr::MIFlag::NoFlags)
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return false;
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for (auto MIB : OutMIs)
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MIB.setMIFlags(Flags);
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return true;
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};
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while (true) {
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assert(CurrentIdx != ~0u && "Invalid MatchTable index");
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int64_t MatcherOpcode = MatchTable[CurrentIdx++];
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@ -1065,6 +1075,7 @@ bool InstructionSelector::executeMatchTable(
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case GIR_Done:
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DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
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dbgs() << CurrentIdx << ": GIR_Done\n");
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propagateFlags(OutMIs);
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return true;
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default:
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@ -71,12 +71,12 @@ body: |
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; CHECK: BR %18
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; CHECK: bb.2.sw.bb:
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; CHECK: successors: %bb.4(0x80000000)
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; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 42, 0
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; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = nsw ADDWri [[COPY]], 42, 0
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; CHECK: B %bb.4
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; CHECK: bb.3.sw.bb1:
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; CHECK: successors: %bb.4(0x80000000)
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 3
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; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[MOVi32imm]], $wzr
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; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = nsw MADDWrrr [[COPY]], [[MOVi32imm]], $wzr
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; CHECK: bb.4.return:
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; CHECK: [[PHI:%[0-9]+]]:gpr32 = PHI [[MADDWrrr]], %bb.3, [[ADDWri]], %bb.2, [[COPY1]], %bb.0, [[COPY2]], %bb.1
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; CHECK: $w0 = COPY [[PHI]]
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