Add the ability to emit register file enums

llvm-svn: 7471

llvm/support/tools/TableGen/RegisterInfoEmitter.cpp

@@ -8,6 +8,7 @@
 
 #include "RegisterInfoEmitter.h"
 #include "Record.h"
+#include <set>
 
 static void EmitSourceHeader(const std::string &Desc, std::ostream &o) {
   o << "//===- TableGen'erated file -------------------------------------*-"
@@ -16,6 +17,29 @@ static void EmitSourceHeader(const std::string &Desc, std::ostream &o) {
        "----------------------------------===//\n\n";
 }
 
+// runEnums - Print out enum values for all of the registers.
+void RegisterInfoEmitter::runEnums(std::ostream &OS) {
+  std::vector<Record*> Registers = Records.getAllDerivedDefinitions("Register");
+
+  if (Registers.size() == 0)
+    throw std::string("No 'Register' subclasses defined!");
+
+  std::string Namespace = Registers[0]->getValueAsString("Namespace");
+
+  EmitSourceHeader("Target Register Enum Values", OS);
+
+  if (!Namespace.empty())
+    OS << "namespace " << Namespace << " {\n";
+  OS << "  enum {\n    NoRegister,\n";
+
+  for (unsigned i = 0, e = Registers.size(); i != e; ++i)
+    OS << "    " << Registers[i]->getName() << ",\n";
+  
+  OS << "  };\n";
+  if (!Namespace.empty())
+    OS << "}\n";
+}
+
 void RegisterInfoEmitter::runHeader(std::ostream &OS) {
   std::vector<Record*> RegisterInfos =
     Records.getAllDerivedDefinitions("RegisterInfo");
@@ -27,14 +51,37 @@ void RegisterInfoEmitter::runHeader(std::ostream &OS) {
 
   std::string ClassName = RegisterInfos[0]->getValueAsString("ClassName");
 
-  OS << "#include \"llvm/CodeGen/MRegisterInfo.h\"\n\n";
+  OS << "#include \"llvm/Target/MRegisterInfo.h\"\n\n";
 
-  OS << "struct " << ClassName << ": public MRegisterInfo {\n"
+  OS << "struct " << ClassName << " : public MRegisterInfo {\n"
      << "  " << ClassName << "();\n"
      << "  const unsigned* getCalleeSaveRegs() const;\n"
      << "};\n\n";
 }
 
-void RegisterInfoEmitter::run(std::ostream &o) {
+// RegisterInfoEmitter::run - Main register file description emitter.
+//
+void RegisterInfoEmitter::run(std::ostream &OS) {
+  EmitSourceHeader("Register Information Source Fragment", OS);
 
+  // Start out by emitting each of the register classes... to do this, we build
+  // a set of registers which belong to a register class, this is to ensure that
+  // each register is only in a single register class.
+  //
+  std::vector<Record*> RegisterClasses =
+    Records.getAllDerivedDefinitions("RegisterClass");
+
+  std::set<Record*> RegistersFound;
+
+  // Loop over all of the register classes... emitting each one.
+  OS << "namespace {     // Register classes...\n";
+  std::vector<std::string> RegisterClassNames;
+  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
+    Record *RC = RegisterClasses[rc];
+    std::string Name = RC->getName();
+    //if (Name[
+
+  }
+
+  OS << "}\n";         // End of anonymous namespace...
 }

llvm/support/tools/TableGen/RegisterInfoEmitter.h

@@ -22,6 +22,9 @@ public:
 
   // runHeader - Emit a header fragment for the register info emitter.
   void runHeader(std::ostream &o);
+
+  // runEnums - Print out enum values for all of the registers.
+  void runEnums(std::ostream &o);
 private:
 };
 

llvm/support/tools/TableGen/TableGen.cpp

@@ -19,7 +19,7 @@
 enum ActionType {
   PrintRecords,
   GenEmitter,
-  GenRegister, GenRegisterHeader,
+  GenRegisterEnums, GenRegister, GenRegisterHeader,
   PrintEnums,
   Parse,
 };
@@ -31,6 +31,8 @@ namespace {
                                "Print all records to stdout (default)"),
                     clEnumValN(GenEmitter, "gen-emitter",
                                "Generate machine code emitter"),
+                    clEnumValN(GenRegisterEnums, "gen-register-enums",
+                               "Generate enum values for registers"),
                     clEnumValN(GenRegister, "gen-register-desc",
                                "Generate a register info description"),
                     clEnumValN(GenRegisterHeader, "gen-register-desc-header",
@@ -411,6 +413,9 @@ int main(int argc, char **argv) {
     case GenEmitter:
       CodeEmitterGen(Records).run(*Out);
       break;
+    case GenRegisterEnums:
+      RegisterInfoEmitter(Records).runEnums(*Out);
+      break;
     case GenRegister:
       RegisterInfoEmitter(Records).run(*Out);
       break;