forked from OSchip/llvm-project
[x86][icelake][vaes]
added vaes feature recognition added intrinsics support for vaes instructions, matching a similar work on the backend (D40078) _mm256_aesenc_epi128 _mm512_aesenc_epi128 _mm256_aesenclast_epi128 _mm512_aesenclast_epi128 _mm256_aesdec_epi128 _mm512_aesdec_epi128 _mm256_aesdeclast_epi128 _mm512_aesdeclast_epi128 llvm-svn: 321474
This commit is contained in:
Coby Tayree
parent
a0ab8d7a58
commit
a1e5f0c339
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@ -429,6 +429,16 @@ TARGET_BUILTIN(__builtin_ia32_aesdeclast128, "V2LLiV2LLiV2LLi", "", "aes")
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TARGET_BUILTIN(__builtin_ia32_aesimc128, "V2LLiV2LLi", "", "aes")
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TARGET_BUILTIN(__builtin_ia32_aeskeygenassist128, "V2LLiV2LLiIc", "", "aes")
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// VAES
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TARGET_BUILTIN(__builtin_ia32_aesenc256, "V4LLiV4LLiV4LLi", "", "vaes")
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TARGET_BUILTIN(__builtin_ia32_aesenc512, "V8LLiV8LLiV8LLi", "", "avx512f,vaes")
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TARGET_BUILTIN(__builtin_ia32_aesenclast256, "V4LLiV4LLiV4LLi", "", "vaes")
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TARGET_BUILTIN(__builtin_ia32_aesenclast512, "V8LLiV8LLiV8LLi", "", "avx512f,vaes")
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TARGET_BUILTIN(__builtin_ia32_aesdec256, "V4LLiV4LLiV4LLi", "", "vaes")
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TARGET_BUILTIN(__builtin_ia32_aesdec512, "V8LLiV8LLiV8LLi", "", "avx512f,vaes")
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TARGET_BUILTIN(__builtin_ia32_aesdeclast256, "V4LLiV4LLiV4LLi", "", "vaes")
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TARGET_BUILTIN(__builtin_ia32_aesdeclast512, "V8LLiV8LLiV8LLi", "", "avx512f,vaes")
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// CLMUL
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TARGET_BUILTIN(__builtin_ia32_pclmulqdq128, "V2LLiV2LLiV2LLiIc", "", "pclmul")
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@ -2543,6 +2543,8 @@ def msha : Flag<["-"], "msha">, Group<m_x86_Features_Group>;
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def mno_sha : Flag<["-"], "mno-sha">, Group<m_x86_Features_Group>;
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def mtbm : Flag<["-"], "mtbm">, Group<m_x86_Features_Group>;
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def mno_tbm : Flag<["-"], "mno-tbm">, Group<m_x86_Features_Group>;
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def mvaes : Flag<["-"], "mvaes">, Group<m_x86_Features_Group>;
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def mno_vaes : Flag<["-"], "mno-vaes">, Group<m_x86_Features_Group>;
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def mxop : Flag<["-"], "mxop">, Group<m_x86_Features_Group>;
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def mno_xop : Flag<["-"], "mno-xop">, Group<m_x86_Features_Group>;
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def mxsave : Flag<["-"], "mxsave">, Group<m_x86_Features_Group>;
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@ -132,6 +132,7 @@ bool X86TargetInfo::initFeatureMap(
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break;
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case CK_Icelake:
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setFeatureEnabledImpl(Features, "vaes", true);
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// TODO: Add icelake features here.
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LLVM_FALLTHROUGH;
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case CK_Cannonlake:
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@ -460,7 +461,7 @@ void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
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LLVM_FALLTHROUGH;
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case AVX:
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Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
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Features["xsaveopt"] = false;
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Features["xsaveopt"] = Features["vaes"] = false;
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setXOPLevel(Features, FMA4, false);
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LLVM_FALLTHROUGH;
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case AVX2:
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@ -572,6 +573,13 @@ void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
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} else if (Name == "aes") {
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if (Enabled)
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setSSELevel(Features, SSE2, Enabled);
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else
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Features["vaes"] = false;
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} else if (Name == "vaes") {
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if (Enabled) {
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setSSELevel(Features, AVX, Enabled);
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Features["aes"] = true;
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}
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} else if (Name == "pclmul") {
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if (Enabled)
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setSSELevel(Features, SSE2, Enabled);
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@ -636,6 +644,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
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if (Feature == "+aes") {
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HasAES = true;
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} else if (Feature == "+vaes") {
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HasVAES = true;
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} else if (Feature == "+pclmul") {
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HasPCLMUL = true;
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} else if (Feature == "+lzcnt") {
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@ -934,6 +944,9 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
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if (HasAES)
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Builder.defineMacro("__AES__");
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if (HasVAES)
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Builder.defineMacro("__VAES__");
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if (HasPCLMUL)
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Builder.defineMacro("__PCLMUL__");
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@ -1185,6 +1198,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
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.Case("sse4.2", true)
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.Case("sse4a", true)
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.Case("tbm", true)
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.Case("vaes", true)
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.Case("x87", true)
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.Case("xop", true)
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.Case("xsave", true)
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@ -1249,6 +1263,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
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.Case("sse4.2", SSELevel >= SSE42)
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.Case("sse4a", XOPLevel >= SSE4A)
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.Case("tbm", HasTBM)
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.Case("vaes", HasVAES)
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.Case("x86", true)
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.Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
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.Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
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@ -48,6 +48,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
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enum XOPEnum { NoXOP, SSE4A, FMA4, XOP } XOPLevel = NoXOP;
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bool HasAES = false;
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bool HasVAES = false;
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bool HasPCLMUL = false;
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bool HasLZCNT = false;
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bool HasRDRND = false;
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@ -82,6 +82,7 @@ set(files
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tmmintrin.h
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unwind.h
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vadefs.h
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vaesintrin.h
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varargs.h
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vecintrin.h
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wmmintrin.h
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@ -208,6 +208,10 @@ _mm256_cvtph_ps(__m128i __a)
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#include <pkuintrin.h>
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#endif
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#if !defined(_MSC_VER) || __has_feature(modules) || defined(__VAES__)
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#include <vaesintrin.h>
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#endif
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#if !defined(_MSC_VER) || __has_feature(modules) || defined(__RDRND__)
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static __inline__ int __attribute__((__always_inline__, __nodebug__, __target__("rdrnd")))
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_rdrand16_step(unsigned short *__p)
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@ -0,0 +1,98 @@
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/*===------------------ vaesintrin.h - VAES intrinsics ---------------------===
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*
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*===-----------------------------------------------------------------------===
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*/
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#ifndef __IMMINTRIN_H
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#error "Never use <vaesintrin.h> directly; include <immintrin.h> instead."
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#endif
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#ifndef __VAESINTRIN_H
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#define __VAESINTRIN_H
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/* Default attributes for YMM forms. */
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#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("vaes")))
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/* Default attributes for ZMM forms. */
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#define __DEFAULT_FN_ATTRS_F __attribute__((__always_inline__, __nodebug__, __target__("avx512f,vaes")))
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static __inline__ __m256i __DEFAULT_FN_ATTRS
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_mm256_aesenc_epi128(__m256i __A, __m256i __B)
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{
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return (__m256i) __builtin_ia32_aesenc256((__v4di) __A,
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(__v4di) __B);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS_F
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_mm512_aesenc_epi128(__m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_aesenc512((__v8di) __A,
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(__v8di) __B);
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}
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static __inline__ __m256i __DEFAULT_FN_ATTRS
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_mm256_aesdec_epi128(__m256i __A, __m256i __B)
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{
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return (__m256i) __builtin_ia32_aesdec256((__v4di) __A,
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(__v4di) __B);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS_F
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_mm512_aesdec_epi128(__m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_aesdec512((__v8di) __A,
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(__v8di) __B);
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}
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static __inline__ __m256i __DEFAULT_FN_ATTRS
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_mm256_aesenclast_epi128(__m256i __A, __m256i __B)
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{
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return (__m256i) __builtin_ia32_aesenclast256((__v4di) __A,
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(__v4di) __B);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS_F
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_mm512_aesenclast_epi128(__m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_aesenclast512((__v8di) __A,
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(__v8di) __B);
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}
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static __inline__ __m256i __DEFAULT_FN_ATTRS
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_mm256_aesdeclast_epi128(__m256i __A, __m256i __B)
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{
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return (__m256i) __builtin_ia32_aesdeclast256((__v4di) __A,
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(__v4di) __B);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS_F
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_mm512_aesdeclast_epi128(__m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_aesdeclast512((__v8di) __A,
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(__v8di) __B);
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}
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#undef __DEFAULT_FN_ATTRS
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#undef __DEFAULT_FN_ATTRS_F
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#endif
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@ -38,9 +38,9 @@ int __attribute__((target("arch=lakemont,mmx"))) lake(int a) { return 4; }
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// CHECK: lake{{.*}} #7
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// CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+x87"
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// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
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// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+x87,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vl,-avx512vpopcntdq,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop,-xsave,-xsaveopt"
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// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+x87,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vl,-avx512vpopcntdq,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-xop,-xsave,-xsaveopt"
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// CHECK: #3 = {{.*}}"target-cpu"="i686" "target-features"="+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87"
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// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+x87,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vl,-avx512vpopcntdq,-f16c,-fma,-fma4,-sse4.1,-sse4.2,-xop,-xsave,-xsaveopt"
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// CHECK: #5 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-aes"
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// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+x87,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vl,-avx512vpopcntdq,-f16c,-fma,-fma4,-sse4.1,-sse4.2,-vaes,-xop,-xsave,-xsaveopt"
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// CHECK: #5 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-aes,-vaes"
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// CHECK: #6 = {{.*}}"target-cpu"="i686" "target-features"="+x87,-3dnow,-3dnowa,-mmx"
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// CHECK: #7 = {{.*}}"target-cpu"="lakemont" "target-features"="+mmx"
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@ -0,0 +1,55 @@
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// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +vaes -emit-llvm -o - | FileCheck %s --check-prefix AVX
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// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-apple-darwin -DAVX512 -target-feature +vaes -target-feature +avx512f -emit-llvm -o - | FileCheck %s --check-prefixes AVX,AVX512
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#include <immintrin.h>
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__m256i test_mm256_aesenc_epi128(__m256i __A, __m256i __B) {
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// AVX-LABEL: @test_mm256_aesenc_epi128
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// AVX: @llvm.x86.aesni.aesenc.256
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return _mm256_aesenc_epi128(__A, __B);
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}
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__m256i test_mm256_aesenclast_epi128(__m256i __A, __m256i __B) {
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// AVX-LABEL: @test_mm256_aesenclast_epi128
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// AVX: @llvm.x86.aesni.aesenclast.256
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return _mm256_aesenclast_epi128(__A, __B);
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}
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__m256i test_mm256_aesdec_epi128(__m256i __A, __m256i __B) {
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// AVX-LABEL: @test_mm256_aesdec_epi128
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// AVX: @llvm.x86.aesni.aesdec.256
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return _mm256_aesdec_epi128(__A, __B);
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}
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__m256i test_mm256_aesdeclast_epi128(__m256i __A, __m256i __B) {
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// AVX-LABEL: @test_mm256_aesdeclast_epi128
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// AVX: @llvm.x86.aesni.aesdeclast.256
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return _mm256_aesdeclast_epi128(__A, __B);
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}
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#ifdef AVX512
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__m512i test_mm512_aesenc_epi128(__m512i __A, __m512i __B) {
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// AVX512-LABEL: @test_mm512_aesenc_epi128
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// AVX512: @llvm.x86.aesni.aesenc.512
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return _mm512_aesenc_epi128(__A, __B);
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}
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__m512i test_mm512_aesenclast_epi128(__m512i __A, __m512i __B) {
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// AVX512-LABEL: @test_mm512_aesenclast_epi128
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// AVX512: @llvm.x86.aesni.aesenclast.512
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return _mm512_aesenclast_epi128(__A, __B);
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}
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__m512i test_mm512_aesdec_epi128(__m512i __A, __m512i __B) {
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// AVX512-LABEL: @test_mm512_aesdec_epi128
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// AVX512: @llvm.x86.aesni.aesdec.512
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return _mm512_aesdec_epi128(__A, __B);
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}
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__m512i test_mm512_aesdeclast_epi128(__m512i __A, __m512i __B) {
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// AVX512-LABEL: @test_mm512_aesdeclast_epi128
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// AVX512: @llvm.x86.aesni.aesdeclast.512
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return _mm512_aesdeclast_epi128(__A, __B);
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}
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#endif
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@ -94,3 +94,9 @@
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// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-clzero %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-CLZERO %s
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// CLZERO: "-target-feature" "+clzero"
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// NO-CLZERO: "-target-feature" "-clzero"
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// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mvaes %s -### -o %t.o 2>&1 | FileCheck -check-prefix=VAES %s
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// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-vaes %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-VAES %s
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// VAES: "-target-feature" "+vaes"
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// NO-VAES: "-target-feature" "-vaes"
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@ -1079,6 +1079,7 @@
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// CHECK_ICL_M32: #define __SSE4_2__ 1
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// CHECK_ICL_M32: #define __SSE__ 1
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// CHECK_ICL_M32: #define __SSSE3__ 1
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// CHECK_ICL_M32: #define __VAES__ 1
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// CHECK_ICL_M32: #define __XSAVEC__ 1
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// CHECK_ICL_M32: #define __XSAVEOPT__ 1
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// CHECK_ICL_M32: #define __XSAVES__ 1
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@ -1124,6 +1125,7 @@
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// CHECK_ICL_M64: #define __SSE4_2__ 1
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// CHECK_ICL_M64: #define __SSE__ 1
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// CHECK_ICL_M64: #define __SSSE3__ 1
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// CHECK_ICL_M64: #define __VAES__ 1
|
||||
// CHECK_ICL_M64: #define __XSAVEC__ 1
|
||||
// CHECK_ICL_M64: #define __XSAVEOPT__ 1
|
||||
// CHECK_ICL_M64: #define __XSAVES__ 1
|
||||
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|||
|
|
@ -368,3 +368,14 @@
|
|||
// RUN: %clang -target i386-unknown-unknown -march=atom -mclflushopt -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=CLFLUSHOPT %s
|
||||
|
||||
// CLFLUSHOPT: #define __CLFLUSHOPT__ 1
|
||||
|
||||
// RUN: %clang -target i386-unknown-unknown -march=atom -mvaes -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=VAES %s
|
||||
|
||||
// VAES: #define __AES__ 1
|
||||
// VAES: #define __VAES__ 1
|
||||
|
||||
// RUN: %clang -target i386-unknown-unknown -march=atom -mvaes -mno-aes -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=VAESNOAES %s
|
||||
|
||||
// VAESNOAES-NOT: #define __AES__ 1
|
||||
// VAESNOAES-NOT: #define __VAES__ 1
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue