forked from OSchip/llvm-project
[SVE] Lower fixed length VECREDUCE_SEQ_FADD operation
Differential Revision: https://reviews.llvm.org/D89162
This commit is contained in:
parent
f98bb414f5
commit
a1cc274cb3
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@ -471,6 +471,10 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
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Node->getValueType(0), Scale);
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break;
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}
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case ISD::VECREDUCE_SEQ_FADD:
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Action = TLI.getOperationAction(Node->getOpcode(),
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Node->getOperand(1).getValueType());
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break;
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case ISD::SINT_TO_FP:
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case ISD::UINT_TO_FP:
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case ISD::VECREDUCE_ADD:
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@ -1119,6 +1119,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::VECREDUCE_SMIN, MVT::v2i64, Custom);
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setOperationAction(ISD::VECREDUCE_UMAX, MVT::v2i64, Custom);
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setOperationAction(ISD::VECREDUCE_UMIN, MVT::v2i64, Custom);
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// Int operations with no NEON support.
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for (auto VT : {MVT::v8i8, MVT::v16i8, MVT::v4i16, MVT::v8i16,
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MVT::v2i32, MVT::v4i32, MVT::v2i64}) {
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setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
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@ -1126,6 +1128,11 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
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}
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// FP operations with no NEON support.
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for (auto VT : {MVT::v4f16, MVT::v8f16, MVT::v2f32, MVT::v4f32,
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MVT::v1f64, MVT::v2f64})
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setOperationAction(ISD::VECREDUCE_SEQ_FADD, VT, Custom);
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// Use SVE for vectors with more than 2 elements.
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for (auto VT : {MVT::v4f16, MVT::v8f16, MVT::v4f32})
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setOperationAction(ISD::VECREDUCE_FADD, VT, Custom);
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@ -1266,6 +1273,7 @@ void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) {
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setOperationAction(ISD::VECREDUCE_ADD, VT, Custom);
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setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
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setOperationAction(ISD::VECREDUCE_FADD, VT, Custom);
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setOperationAction(ISD::VECREDUCE_SEQ_FADD, VT, Custom);
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setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
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setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
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setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
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@ -3964,6 +3972,8 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
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return LowerINTRINSIC_WO_CHAIN(Op, DAG);
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case ISD::STORE:
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return LowerSTORE(Op, DAG);
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case ISD::VECREDUCE_SEQ_FADD:
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return LowerVECREDUCE_SEQ_FADD(Op, DAG);
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case ISD::VECREDUCE_ADD:
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case ISD::VECREDUCE_AND:
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case ISD::VECREDUCE_OR:
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@ -16257,6 +16267,34 @@ SDValue AArch64TargetLowering::LowerToScalableOp(SDValue Op,
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return convertFromScalableVector(DAG, VT, ScalableRes);
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}
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SDValue AArch64TargetLowering::LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp,
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SelectionDAG &DAG) const {
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SDLoc DL(ScalarOp);
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SDValue AccOp = ScalarOp.getOperand(0);
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SDValue VecOp = ScalarOp.getOperand(1);
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EVT SrcVT = VecOp.getValueType();
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EVT ResVT = SrcVT.getVectorElementType();
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// Only fixed length FADDA handled for now.
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if (!useSVEForFixedLengthVectorVT(SrcVT, /*OverrideNEON=*/true))
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return SDValue();
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SDValue Pg = getPredicateForVector(DAG, DL, SrcVT);
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EVT ContainerVT = getContainerForFixedLengthVector(DAG, SrcVT);
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SDValue Zero = DAG.getConstant(0, DL, MVT::i64);
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// Convert operands to Scalable.
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AccOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ContainerVT,
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DAG.getUNDEF(ContainerVT), AccOp, Zero);
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VecOp = convertToScalableVector(DAG, ContainerVT, VecOp);
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// Perform reduction.
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SDValue Rdx = DAG.getNode(AArch64ISD::FADDA_PRED, DL, ContainerVT,
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Pg, AccOp, VecOp);
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return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Rdx, Zero);
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}
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SDValue AArch64TargetLowering::LowerFixedLengthReductionToSVE(unsigned Opcode,
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SDValue ScalarOp, SelectionDAG &DAG) const {
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SDLoc DL(ScalarOp);
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@ -780,6 +780,14 @@ public:
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return !useSVEForFixedLengthVectors();
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}
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// FIXME: Move useSVEForFixedLengthVectors*() back to private scope once
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// reduction legalization is complete.
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bool useSVEForFixedLengthVectors() const;
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// Normally SVE is only used for byte size vectors that do not fit within a
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// NEON vector. This changes when OverrideNEON is true, allowing SVE to be
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// used for 64bit and 128bit vectors as well.
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bool useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON = false) const;
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private:
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/// Keep a pointer to the AArch64Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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@ -935,6 +943,7 @@ private:
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SDValue LowerFixedLengthVectorIntExtendToSVE(SDValue Op,
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SelectionDAG &DAG) const;
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SDValue LowerFixedLengthVectorLoadToSVE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp, SelectionDAG &DAG) const;
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SDValue LowerFixedLengthReductionToSVE(unsigned Opcode, SDValue ScalarOp,
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SelectionDAG &DAG) const;
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SDValue LowerFixedLengthVectorSelectToSVE(SDValue Op, SelectionDAG &DAG) const;
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@ -1006,12 +1015,6 @@ private:
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bool shouldLocalize(const MachineInstr &MI,
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const TargetTransformInfo *TTI) const override;
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bool useSVEForFixedLengthVectors() const;
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// Normally SVE is only used for byte size vectors that do not fit within a
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// NEON vector. This changes when OverrideNEON is true, allowing SVE to be
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// used for 64bit and 128bit vectors as well.
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bool useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON = false) const;
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};
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namespace AArch64 {
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@ -222,7 +222,15 @@ public:
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bool shouldExpandReduction(const IntrinsicInst *II) const {
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switch (II->getIntrinsicID()) {
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case Intrinsic::vector_reduce_fadd:
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case Intrinsic::vector_reduce_fadd: {
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Value *VecOp = II->getArgOperand(1);
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EVT VT = TLI->getValueType(getDataLayout(), VecOp->getType());
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if (ST->hasSVE() &&
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TLI->useSVEForFixedLengthVectorVT(VT, /*OverrideNEON=*/true))
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return false;
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return !II->getFastMathFlags().allowReassoc();
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}
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case Intrinsic::vector_reduce_fmul:
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// We don't have legalization support for ordered FP reductions.
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return !II->getFastMathFlags().allowReassoc();
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@ -20,6 +20,214 @@ target triple = "aarch64-unknown-linux-gnu"
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; Don't use SVE when its registers are no bigger than NEON.
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; NO_SVE-NOT: ptrue
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;
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; FADDA
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;
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; No single instruction NEON support. Use SVE.
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define half @fadda_v4f16(half %start, <4 x half> %a) #0 {
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; CHECK-LABEL: fadda_v4f16:
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; CHECK: ptrue [[PG:p[0-9]+]].h, vl4
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; CHECK-NEXT: fadda h0, [[PG]], h0, z1.h
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; CHECK-NEXT: ret
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%res = call half @llvm.vector.reduce.fadd.v4f16(half %start, <4 x half> %a)
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ret half %res
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}
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; No single instruction NEON support. Use SVE.
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define half @fadda_v8f16(half %start, <8 x half> %a) #0 {
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; CHECK-LABEL: fadda_v8f16:
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; CHECK: ptrue [[PG:p[0-9]+]].h, vl8
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; CHECK-NEXT: fadda h0, [[PG]], h0, z1.h
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; CHECK-NEXT: ret
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%res = call half @llvm.vector.reduce.fadd.v8f16(half %start, <8 x half> %a)
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ret half %res
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}
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define half @fadda_v16f16(half %start, <16 x half>* %a) #0 {
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; CHECK-LABEL: fadda_v16f16:
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; CHECK: ptrue [[PG:p[0-9]+]].h, vl16
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; CHECK-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
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; CHECK-NEXT: fadda h0, [[PG]], h0, [[OP]].h
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; CHECK-NEXT: ret
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%op = load <16 x half>, <16 x half>* %a
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%res = call half @llvm.vector.reduce.fadd.v16f16(half %start, <16 x half> %op)
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ret half %res
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}
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define half @fadda_v32f16(half %start, <32 x half>* %a) #0 {
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; CHECK-LABEL: fadda_v32f16:
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; VBITS_GE_512: ptrue [[PG:p[0-9]+]].h, vl32
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; VBITS_GE_512-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
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; VBITS_GE_512-NEXT: fadda h0, [[PG]], h0, [[OP]].h
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; VBITS_GE_512-NEXT: ret
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; Ensure sensible type legalisation.
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; VBITS_EQ_256-COUNT-32: fadd
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; VBITS_EQ_256: ret
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%op = load <32 x half>, <32 x half>* %a
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%res = call half @llvm.vector.reduce.fadd.v32f16(half %start, <32 x half> %op)
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ret half %res
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}
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define half @fadda_v64f16(half %start, <64 x half>* %a) #0 {
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; CHECK-LABEL: fadda_v64f16:
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; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].h, vl64
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; VBITS_GE_1024-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
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; VBITS_GE_1024-NEXT: fadda h0, [[PG]], h0, [[OP]].h
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; VBITS_GE_1024-NEXT: ret
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%op = load <64 x half>, <64 x half>* %a
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%res = call half @llvm.vector.reduce.fadd.v64f16(half %start, <64 x half> %op)
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ret half %res
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}
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define half @fadda_v128f16(half %start, <128 x half>* %a) #0 {
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; CHECK-LABEL: fadda_v128f16:
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; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].h, vl128
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; VBITS_GE_2048-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
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; VBITS_GE_2048-NEXT: fadda h0, [[PG]], h0, [[OP]].h
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; VBITS_GE_2048-NEXT: ret
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%op = load <128 x half>, <128 x half>* %a
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%res = call half @llvm.vector.reduce.fadd.v128f16(half %start, <128 x half> %op)
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ret half %res
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}
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; No single instruction NEON support. Use SVE.
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define float @fadda_v2f32(float %start, <2 x float> %a) #0 {
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; CHECK-LABEL: fadda_v2f32:
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; CHECK: ptrue [[PG:p[0-9]+]].s, vl2
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; CHECK-NEXT: fadda s0, [[PG]], s0, z1.s
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; CHECK-NEXT: ret
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%res = call float @llvm.vector.reduce.fadd.v2f32(float %start, <2 x float> %a)
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ret float %res
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}
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; No single instruction NEON support. Use SVE.
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define float @fadda_v4f32(float %start, <4 x float> %a) #0 {
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; CHECK-LABEL: fadda_v4f32:
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; CHECK: ptrue [[PG:p[0-9]+]].s, vl4
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; CHECK-NEXT: fadda s0, [[PG]], s0, z1.s
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; CHECK-NEXT: ret
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%res = call float @llvm.vector.reduce.fadd.v4f32(float %start, <4 x float> %a)
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ret float %res
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}
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define float @fadda_v8f32(float %start, <8 x float>* %a) #0 {
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; CHECK-LABEL: fadda_v8f32:
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; CHECK: ptrue [[PG:p[0-9]+]].s, vl8
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; CHECK-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
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; CHECK-NEXT: fadda s0, [[PG]], s0, [[OP]].s
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; CHECK-NEXT: ret
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%op = load <8 x float>, <8 x float>* %a
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%res = call float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %op)
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ret float %res
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}
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define float @fadda_v16f32(float %start, <16 x float>* %a) #0 {
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; CHECK-LABEL: fadda_v16f32:
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; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl16
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; VBITS_GE_512-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
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; VBITS_GE_512-NEXT: fadda s0, [[PG]], s0, [[OP]].s
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; VBITS_GE_512-NEXT: ret
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; Ensure sensible type legalisation.
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; VBITS_EQ_256-COUNT-16: fadd
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; VBITS_EQ_256: ret
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%op = load <16 x float>, <16 x float>* %a
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%res = call float @llvm.vector.reduce.fadd.v16f32(float %start, <16 x float> %op)
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ret float %res
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}
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define float @fadda_v32f32(float %start, <32 x float>* %a) #0 {
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; CHECK-LABEL: fadda_v32f32:
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; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].s, vl32
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; VBITS_GE_1024-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
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; VBITS_GE_1024-NEXT: fadda s0, [[PG]], s0, [[OP]].s
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; VBITS_GE_1024-NEXT: ret
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%op = load <32 x float>, <32 x float>* %a
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%res = call float @llvm.vector.reduce.fadd.v32f32(float %start, <32 x float> %op)
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ret float %res
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}
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define float @fadda_v64f32(float %start, <64 x float>* %a) #0 {
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; CHECK-LABEL: fadda_v64f32:
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; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].s, vl64
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; VBITS_GE_2048-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
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; VBITS_GE_2048-NEXT: fadda s0, [[PG]], s0, [[OP]].s
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; VBITS_GE_2048-NEXT: ret
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%op = load <64 x float>, <64 x float>* %a
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%res = call float @llvm.vector.reduce.fadd.v64f32(float %start, <64 x float> %op)
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ret float %res
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}
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; No single instruction NEON support. Use SVE.
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define double @fadda_v1f64(double %start, <1 x double> %a) #0 {
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; CHECK-LABEL: fadda_v1f64:
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; CHECK: ptrue [[PG:p[0-9]+]].d, vl1
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; CHECK-NEXT: fadda d0, [[PG]], d0, z1.d
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; CHECK-NEXT: ret
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%res = call double @llvm.vector.reduce.fadd.v1f64(double %start, <1 x double> %a)
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ret double %res
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}
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; No single instruction NEON support. Use SVE.
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define double @fadda_v2f64(double %start, <2 x double> %a) #0 {
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; CHECK-LABEL: fadda_v2f64:
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; CHECK: ptrue [[PG:p[0-9]+]].d, vl2
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; CHECK-NEXT: fadda d0, [[PG]], d0, z1.d
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; CHECK-NEXT: ret
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%res = call double @llvm.vector.reduce.fadd.v2f64(double %start, <2 x double> %a)
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ret double %res
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}
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define double @fadda_v4f64(double %start, <4 x double>* %a) #0 {
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; CHECK-LABEL: fadda_v4f64:
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; CHECK: ptrue [[PG:p[0-9]+]].d, vl4
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; CHECK-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
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; CHECK-NEXT: fadda d0, [[PG]], d0, [[OP]].d
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; CHECK-NEXT: ret
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%op = load <4 x double>, <4 x double>* %a
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%res = call double @llvm.vector.reduce.fadd.v4f64(double %start, <4 x double> %op)
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ret double %res
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}
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define double @fadda_v8f64(double %start, <8 x double>* %a) #0 {
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; CHECK-LABEL: fadda_v8f64:
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; VBITS_GE_512: ptrue [[PG:p[0-9]+]].d, vl8
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; VBITS_GE_512-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
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; VBITS_GE_512-NEXT: fadda d0, [[PG]], d0, [[OP]].d
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; VBITS_GE_512-NEXT: ret
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; Ensure sensible type legalisation.
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; VBITS_EQ_256-COUNT-8: fadd
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; VBITS_EQ_256: ret
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%op = load <8 x double>, <8 x double>* %a
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%res = call double @llvm.vector.reduce.fadd.v8f64(double %start, <8 x double> %op)
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ret double %res
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}
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define double @fadda_v16f64(double %start, <16 x double>* %a) #0 {
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; CHECK-LABEL: fadda_v16f64:
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; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].d, vl16
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; VBITS_GE_1024-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
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; VBITS_GE_1024-NEXT: fadda d0, [[PG]], d0, [[OP]].d
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; VBITS_GE_1024-NEXT: ret
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%op = load <16 x double>, <16 x double>* %a
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%res = call double @llvm.vector.reduce.fadd.v16f64(double %start, <16 x double> %op)
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ret double %res
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}
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define double @fadda_v32f64(double %start, <32 x double>* %a) #0 {
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; CHECK-LABEL: fadda_v32f64:
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; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].d, vl32
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; VBITS_GE_2048-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
|
||||
; VBITS_GE_2048-NEXT: fadda d0, [[PG]], d0, [[OP]].d
|
||||
; VBITS_GE_2048-NEXT: ret
|
||||
%op = load <32 x double>, <32 x double>* %a
|
||||
%res = call double @llvm.vector.reduce.fadd.v32f64(double %start, <32 x double> %op)
|
||||
ret double %res
|
||||
}
|
||||
|
||||
;
|
||||
; FADDV
|
||||
;
|
||||
|
|
Loading…
Reference in New Issue