maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[DAGCombiner] Add (sub_sat x, x) -> 0 combine 

llvm-svn: 351073
This commit is contained in:
Simon Pilgrim 2019-01-14 15:43:34 +00:00
parent fa1f518748
commit a1bd4a6ba4
3 changed files with 8 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -2800,6 +2800,10 @@ SDValue DAGCombiner::visitSUBSAT(SDNode *N) {
if (N0.isUndef() || N1.isUndef()) if (N0.isUndef() || N1.isUndef())
return DAG.getConstant(0, DL, VT); return DAG.getConstant(0, DL, VT);
// fold (sub_sat x, x) -> 0
if (N0 == N1)
return DAG.getConstant(0, DL, VT);
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
DAG.isConstantIntBuildVectorOrConstantInt(N1)) { DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
// fold (sub_sat c1, c2) -> c3 // fold (sub_sat c1, c2) -> c3

10
llvm/test/CodeGen/X86/combine-sub-ssat.ll
View File

@ -96,12 +96,6 @@ define i32 @combine_self_i32(i32 %a0) {
; CHECK-LABEL: combine_self_i32: ; CHECK-LABEL: combine_self_i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: movl %edi, %ecx
; CHECK-NEXT: subl %edi, %ecx
; CHECK-NEXT: setns %al
; CHECK-NEXT: addl $2147483647, %eax # imm = 0x7FFFFFFF
; CHECK-NEXT: subl %edi, %edi
; CHECK-NEXT: cmovnol %edi, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%1 = call i32 @llvm.ssub.sat.i32(i32 %a0, i32 %a0) %1 = call i32 @llvm.ssub.sat.i32(i32 %a0, i32 %a0)
ret i32 %1 ret i32 %1
@ -110,12 +104,12 @@ define i32 @combine_self_i32(i32 %a0) {
define <8 x i16> @combine_self_v8i16(<8 x i16> %a0) { define <8 x i16> @combine_self_v8i16(<8 x i16> %a0) {
; SSE-LABEL: combine_self_v8i16: ; SSE-LABEL: combine_self_v8i16:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: psubsw %xmm0, %xmm0 ; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: combine_self_v8i16: ; AVX-LABEL: combine_self_v8i16:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpsubsw %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %a0, <8 x i16> %a0) %1 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %a0, <8 x i16> %a0)
ret <8 x i16> %1 ret <8 x i16> %1

6
llvm/test/CodeGen/X86/combine-sub-usat.ll
View File

@ -96,8 +96,6 @@ define i32 @combine_self_i32(i32 %a0) {
; CHECK-LABEL: combine_self_i32: ; CHECK-LABEL: combine_self_i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: subl %edi, %edi
; CHECK-NEXT: cmovael %edi, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%1 = call i32 @llvm.usub.sat.i32(i32 %a0, i32 %a0) %1 = call i32 @llvm.usub.sat.i32(i32 %a0, i32 %a0)
ret i32 %1 ret i32 %1
@ -106,12 +104,12 @@ define i32 @combine_self_i32(i32 %a0) {
define <8 x i16> @combine_self_v8i16(<8 x i16> %a0) { define <8 x i16> @combine_self_v8i16(<8 x i16> %a0) {
; SSE-LABEL: combine_self_v8i16: ; SSE-LABEL: combine_self_v8i16:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: psubusw %xmm0, %xmm0 ; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: combine_self_v8i16: ; AVX-LABEL: combine_self_v8i16:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpsubusw %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %a0, <8 x i16> %a0) %1 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %a0, <8 x i16> %a0)
ret <8 x i16> %1 ret <8 x i16> %1