forked from OSchip/llvm-project
[AMDGPU] Extend constant folding for logical operations
This patch extends existing constant folding in logical operations to handle S_XNOR, S_NAND, S_NOR, S_ANDN2, S_ORN2, V_LSHL_ADD_U32 and V_AND_OR_B32. Also added a couple of tests for existing folds.
This commit is contained in:
Graham Sellers
Matt Arsenault
parent
c41685b16f
commit
a19a56f6a1
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@ -914,6 +914,21 @@ static bool evalBinaryInstruction(unsigned Opcode, int32_t &Result,
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case AMDGPU::S_XOR_B32:
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Result = LHS ^ RHS;
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return true;
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case AMDGPU::S_XNOR_B32:
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Result = ~(LHS ^ RHS);
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return true;
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case AMDGPU::S_NAND_B32:
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Result = ~(LHS & RHS);
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return true;
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case AMDGPU::S_NOR_B32:
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Result = ~(LHS | RHS);
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return true;
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case AMDGPU::S_ANDN2_B32:
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Result = LHS & ~RHS;
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return true;
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case AMDGPU::S_ORN2_B32:
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Result = LHS | ~RHS;
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return true;
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case AMDGPU::V_LSHL_B32_e64:
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case AMDGPU::V_LSHL_B32_e32:
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case AMDGPU::S_LSHL_B32:
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@ -1014,10 +1029,16 @@ static bool tryConstantFoldOp(MachineRegisterInfo &MRI,
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if (!Src0->isImm() && !Src1->isImm())
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return false;
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if (MI->getOpcode() == AMDGPU::V_LSHL_OR_B32) {
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if (MI->getOpcode() == AMDGPU::V_LSHL_OR_B32 ||
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MI->getOpcode() == AMDGPU::V_LSHL_ADD_U32 ||
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MI->getOpcode() == AMDGPU::V_AND_OR_B32) {
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if (Src0->isImm() && Src0->getImm() == 0) {
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// v_lshl_or_b32 0, X, Y -> copy Y
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// v_lshl_or_b32 0, X, K -> v_mov_b32 K
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// v_lshl_add_b32 0, X, Y -> copy Y
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// v_lshl_add_b32 0, X, K -> v_mov_b32 K
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// v_and_or_b32 0, X, Y -> copy Y
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// v_and_or_b32 0, X, K -> v_mov_b32 K
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bool UseCopy = TII->getNamedOperand(*MI, AMDGPU::OpName::src2)->isReg();
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MI->RemoveOperand(Src1Idx);
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MI->RemoveOperand(Src0Idx);
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@ -69,7 +69,7 @@ body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $vgpr0
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%3:vgpr_32 = COPY $vgpr0
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%3:vgpr_32 = COPY $vgpr0
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%4:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
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%13:vgpr_32 = V_ASHRREV_I32_e64 31, %3, implicit $exec
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@ -130,98 +130,6 @@ body: |
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BUFFER_STORE_DWORD_OFFSET killed %13, killed %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec
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S_ENDPGM 0
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...
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---
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# GCN-LABEL: name: v_fold_shl_imm_regimm_32{{$}}
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# GCN: [[VAL0:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 40955904, implicit $exec
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# GCN: FLAT_STORE_DWORD %10, [[VAL0]],
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# GCN: [[VAL1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 24, implicit $exec
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# GCN: FLAT_STORE_DWORD %10, [[VAL1]],
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# GCN: [[VAL2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
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# GCN: FLAT_STORE_DWORD %10, [[VAL2]],
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# GCN: [[VAL3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 24, implicit $exec
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# GCN: FLAT_STORE_DWORD %10, [[VAL3]],
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# GCN: [[VAL4:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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# GCN: FLAT_STORE_DWORD %10, [[VAL4]],
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# GCN: [[VAL5:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
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# GCN: FLAT_STORE_DWORD %10, [[VAL5]],
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# GCN: [[VAL6:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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# GCN: FLAT_STORE_DWORD %10, [[VAL6]],
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# GCN: [[VAL7:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
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# GCN: FLAT_STORE_DWORD %10, [[VAL7]],
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# GCN: [[VAL8:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 7927808, implicit $exec
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# GCN: FLAT_STORE_DWORD %10, [[VAL8]],
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# GCN: [[VAL9:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -8, implicit $exec
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# GCN: FLAT_STORE_DWORD %10, [[VAL9]],
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name: v_fold_shl_imm_regimm_32
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tracksRegLiveness: true
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liveins:
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- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
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- { reg: '$vgpr0', virtual-reg: '%2' }
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $vgpr0
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%2:vgpr_32 = COPY $vgpr0
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%3:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, addrspace 4)
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%15:vgpr_32 = V_ASHRREV_I32_e64 31, %2, implicit $exec
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%16:vreg_64 = REG_SEQUENCE %2, %subreg.hi16, %15, %subreg.lo16
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%17:vreg_64 = V_LSHLREV_B64 2, killed %16, implicit $exec
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%9:sreg_32_xm0 = COPY %3.sub1
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%21:vgpr_32 = V_ADD_I32_e32 %3.sub0, %17.sub0, implicit-def $vcc, implicit $exec
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%19:vgpr_32 = COPY killed %9
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%18:vgpr_32 = V_ADDC_U32_e32 %17.sub1, %19, implicit-def $vcc, implicit $vcc, implicit $exec
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%20:vreg_64 = REG_SEQUENCE %21, %subreg.hi16, killed %18, %subreg.lo16
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%10:vgpr_32 = V_MOV_B32_e32 9999, implicit $exec
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%24:vgpr_32 = V_MOV_B32_e32 3871, implicit $exec
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%6:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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%7:sreg_32_xm0 = S_MOV_B32 1
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%27:sreg_32_xm0 = S_MOV_B32 -4
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%11:vgpr_32 = V_LSHLREV_B32_e64 12, %10, implicit $exec
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FLAT_STORE_DWORD %20, %11, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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%12:vgpr_32 = V_LSHLREV_B32_e64 %7, 12, implicit $exec
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FLAT_STORE_DWORD %20, %12, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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%13:vgpr_32 = V_LSHL_B32_e64 %7, 12, implicit $exec
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FLAT_STORE_DWORD %20, %13, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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%14:vgpr_32 = V_LSHL_B32_e64 12, %7, implicit $exec
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FLAT_STORE_DWORD %20, %14, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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%15:vgpr_32 = V_LSHL_B32_e64 12, %24, implicit $exec
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FLAT_STORE_DWORD %20, %15, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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%22:vgpr_32 = V_LSHL_B32_e64 %6, 12, implicit $exec
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FLAT_STORE_DWORD %20, %22, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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%23:vgpr_32 = V_LSHL_B32_e64 %6, 32, implicit $exec
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FLAT_STORE_DWORD %20, %23, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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%25:vgpr_32 = V_LSHL_B32_e32 %6, %6, implicit $exec
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FLAT_STORE_DWORD %20, %25, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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%26:vgpr_32 = V_LSHLREV_B32_e32 11, %24, implicit $exec
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FLAT_STORE_DWORD %20, %26, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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%28:vgpr_32 = V_LSHL_B32_e32 %27, %6, implicit $exec
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FLAT_STORE_DWORD %20, %28, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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S_ENDPGM 0
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...
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---
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@ -571,3 +479,489 @@ body: |
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S_ENDPGM 0, implicit %3
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...
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---
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# GCN-LABEL: name: s_fold_andn2_imm_regimm_32{{$}}
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# GCN: [[VAL:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1233024, implicit $exec
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# GCN: BUFFER_STORE_DWORD_OFFSET killed [[VAL]],
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name: s_fold_andn2_imm_regimm_32
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tracksRegLiveness: true
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liveins:
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- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
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%2:sreg_32_xm0 = COPY %1.sub1
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%3:sreg_32_xm0 = COPY %1.sub0
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%4:sreg_32_xm0 = S_MOV_B32 61440
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%5:sreg_32_xm0 = S_MOV_B32 -1
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%6:sgpr_128 = REG_SEQUENCE killed %2, %subreg.sub0, killed %3, %subreg.sub1, killed %4, %subreg.sub2, killed %5, %subreg.sub3
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%7:sreg_32_xm0 = S_MOV_B32 1234567
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%8:sreg_32_xm0 = S_MOV_B32 9999
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%9:sreg_32_xm0 = S_ANDN2_B32 killed %7, killed %8, implicit-def dead $scc
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%10:vgpr_32 = COPY %9
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BUFFER_STORE_DWORD_OFFSET killed %10, killed %6, 0, 0, 0, 0, 0, 0, 0, implicit $exec
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S_ENDPGM 0
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...
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---
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# GCN-LABEL: name: s_fold_or_imm_regimm_32{{$}}
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# GCN: %10:vgpr_32 = V_MOV_B32_e32 1243023, implicit $exec
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# GCN: BUFFER_STORE_DWORD_OFFSET killed %10,
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name: s_fold_or_imm_regimm_32
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alignment: 0
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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liveins:
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- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
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%2:sreg_32_xm0 = COPY %1.sub1
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%3:sreg_32_xm0 = COPY %1.sub0
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%4:sreg_32_xm0 = S_MOV_B32 61440
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%5:sreg_32_xm0 = S_MOV_B32 -1
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%6:sgpr_128 = REG_SEQUENCE killed %2, %subreg.sub0, killed %3, %subreg.sub1, killed %4, %subreg.sub2, killed %5, %subreg.sub3
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%7:sreg_32_xm0 = S_MOV_B32 1234567
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%8:sreg_32_xm0 = S_MOV_B32 9999
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%9:sreg_32_xm0 = S_OR_B32 killed %7, killed %8, implicit-def dead $scc
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%10:vgpr_32 = COPY %9
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BUFFER_STORE_DWORD_OFFSET killed %10, killed %6, 0, 0, 0, 0, 0, 0, 0, implicit $exec
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S_ENDPGM 0
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...
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---
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# GCN-LABEL: name: v_fold_or_imm_regimm_32{{$}}
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# GCN: %14:vgpr_32 = V_MOV_B32_e32 1234903, implicit $exec
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# GCN: FLAT_STORE_DWORD %10, %14,
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# GCN: %15:vgpr_32 = V_MOV_B32_e32 1234903, implicit $exec
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# GCN: FLAT_STORE_DWORD %10, %15
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# GCN: %16:vgpr_32 = V_MOV_B32_e32 1234903, implicit $exec
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# GCN: FLAT_STORE_DWORD %10, %16,
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# GCN: %17:vgpr_32 = V_MOV_B32_e32 1234567, implicit $exec
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# GCN: FLAT_STORE_DWORD %10, %17,
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# GCN: %3:vgpr_32 = V_MOV_B32_e32 63, implicit $exec
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# GCN: FLAT_STORE_DWORD %10, %3,
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name: v_fold_or_imm_regimm_32
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alignment: 0
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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liveins:
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- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
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- { reg: '$vgpr0', virtual-reg: '%3' }
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $vgpr0
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%3:vgpr_32 = COPY $vgpr0
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%4:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
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%13:vgpr_32 = V_ASHRREV_I32_e64 31, %3, implicit $exec
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%14:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %13, %subreg.sub1
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%15:vreg_64 = V_LSHLREV_B64 2, killed %14, implicit $exec
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%5:sreg_32_xm0 = COPY %4.sub1
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%20:vgpr_32 = V_ADD_I32_e32 %4.sub0, %15.sub0, implicit-def $vcc, implicit $exec
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%18:vgpr_32 = COPY killed %5
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%17:vgpr_32 = V_ADDC_U32_e32 %15.sub1, %18, implicit-def $vcc, implicit $vcc, implicit $exec
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%19:vreg_64 = REG_SEQUENCE %20, %subreg.sub0, killed %17, %subreg.sub1
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%6:vgpr_32 = V_MOV_B32_e32 982, implicit $exec
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%8:sreg_32_xm0 = S_MOV_B32 1234567
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%16:vgpr_32 = V_MOV_B32_e32 63, implicit $exec
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%9:vgpr_32 = V_OR_B32_e64 %8, %6, implicit $exec
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FLAT_STORE_DWORD %19, %9, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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%10:vgpr_32 = V_OR_B32_e64 %6, %8, implicit $exec
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FLAT_STORE_DWORD %19, %10, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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%11:vgpr_32 = V_OR_B32_e32 %8, %6, implicit $exec
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FLAT_STORE_DWORD %19, %11, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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%12:vgpr_32 = V_OR_B32_e64 %8, %8, implicit $exec
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FLAT_STORE_DWORD %19, %12, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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%13:vgpr_32 = V_OR_B32_e64 %16, %16, implicit $exec
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FLAT_STORE_DWORD %19, %13, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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S_ENDPGM 0
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...
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---
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# GCN-LABEL: name: s_fold_orn2_imm_regimm_32{{$}}
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# GCN: %10:vgpr_32 = V_MOV_B32_e32 -8457, implicit $exec
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# GCN: BUFFER_STORE_DWORD_OFFSET killed %10,
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name: s_fold_orn2_imm_regimm_32
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alignment: 0
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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liveins:
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- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
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%2:sreg_32_xm0 = COPY %1.sub1
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%3:sreg_32_xm0 = COPY %1.sub0
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%4:sreg_32_xm0 = S_MOV_B32 61440
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%5:sreg_32_xm0 = S_MOV_B32 -1
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%6:sgpr_128 = REG_SEQUENCE killed %2, %subreg.sub0, killed %3, %subreg.sub1, killed %4, %subreg.sub2, killed %5, %subreg.sub3
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%7:sreg_32_xm0 = S_MOV_B32 1234567
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%8:sreg_32_xm0 = S_MOV_B32 9999
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%9:sreg_32_xm0 = S_ORN2_B32 killed %7, killed %8, implicit-def dead $scc
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%10:vgpr_32 = COPY %9
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BUFFER_STORE_DWORD_OFFSET killed %10, killed %6, 0, 0, 0, 0, 0, 0, 0, implicit $exec
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S_ENDPGM 0
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...
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---
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# GCN-LABEL: name: s_fold_nand_imm_regimm_32{{$}}
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# GCN: %10:vgpr_32 = V_MOV_B32_e32 -1544, implicit $exec
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# GCN: BUFFER_STORE_DWORD_OFFSET killed %10,
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name: s_fold_nand_imm_regimm_32
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alignment: 0
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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liveins:
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- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
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%2:sreg_32_xm0 = COPY %1.sub1
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%3:sreg_32_xm0 = COPY %1.sub0
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%4:sreg_32_xm0 = S_MOV_B32 61440
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%5:sreg_32_xm0 = S_MOV_B32 -1
|
||||
%6:sgpr_128 = REG_SEQUENCE killed %2, %subreg.sub0, killed %3, %subreg.sub1, killed %4, %subreg.sub2, killed %5, %subreg.sub3
|
||||
%7:sreg_32_xm0 = S_MOV_B32 1234567
|
||||
%8:sreg_32_xm0 = S_MOV_B32 9999
|
||||
%9:sreg_32_xm0 = S_NAND_B32 killed %7, killed %8, implicit-def dead $scc
|
||||
%10:vgpr_32 = COPY %9
|
||||
BUFFER_STORE_DWORD_OFFSET killed %10, killed %6, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
S_ENDPGM 0
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
# GCN-LABEL: name: s_fold_nor_imm_regimm_32{{$}}
|
||||
# GCN: %10:vgpr_32 = V_MOV_B32_e32 -1243024, implicit $exec
|
||||
# GCN: BUFFER_STORE_DWORD_OFFSET killed %10,
|
||||
name: s_fold_nor_imm_regimm_32
|
||||
alignment: 0
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
tracksRegLiveness: true
|
||||
liveins:
|
||||
- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0_sgpr1
|
||||
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sreg_32_xm0 = COPY %1.sub1
|
||||
%3:sreg_32_xm0 = COPY %1.sub0
|
||||
%4:sreg_32_xm0 = S_MOV_B32 61440
|
||||
%5:sreg_32_xm0 = S_MOV_B32 -1
|
||||
%6:sgpr_128 = REG_SEQUENCE killed %2, %subreg.sub0, killed %3, %subreg.sub1, killed %4, %subreg.sub2, killed %5, %subreg.sub3
|
||||
%7:sreg_32_xm0 = S_MOV_B32 1234567
|
||||
%8:sreg_32_xm0 = S_MOV_B32 9999
|
||||
%9:sreg_32_xm0 = S_NOR_B32 killed %7, killed %8, implicit-def dead $scc
|
||||
%10:vgpr_32 = COPY %9
|
||||
BUFFER_STORE_DWORD_OFFSET killed %10, killed %6, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
S_ENDPGM 0
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
# GCN-LABEL: name: s_fold_xnor_imm_regimm_32{{$}}
|
||||
# GCN: %10:vgpr_32 = V_MOV_B32_e32 -1241481, implicit $exec
|
||||
# GCN: BUFFER_STORE_DWORD_OFFSET killed %10,
|
||||
name: s_fold_xnor_imm_regimm_32
|
||||
alignment: 0
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
tracksRegLiveness: true
|
||||
liveins:
|
||||
- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0_sgpr1
|
||||
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sreg_32_xm0 = COPY %1.sub1
|
||||
%3:sreg_32_xm0 = COPY %1.sub0
|
||||
%4:sreg_32_xm0 = S_MOV_B32 61440
|
||||
%5:sreg_32_xm0 = S_MOV_B32 -1
|
||||
%6:sgpr_128 = REG_SEQUENCE killed %2, %subreg.sub0, killed %3, %subreg.sub1, killed %4, %subreg.sub2, killed %5, %subreg.sub3
|
||||
%7:sreg_32_xm0 = S_MOV_B32 1234567
|
||||
%8:sreg_32_xm0 = S_MOV_B32 9999
|
||||
%9:sreg_32_xm0 = S_XNOR_B32 killed %7, killed %8, implicit-def dead $scc
|
||||
%10:vgpr_32 = COPY %9
|
||||
BUFFER_STORE_DWORD_OFFSET killed %10, killed %6, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
S_ENDPGM 0
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
# GCN-LABEL: name: v_fold_shl_imm_regimm_32{{$}}
|
||||
|
||||
# GCN: %16:vgpr_32 = V_MOV_B32_e32 40955904, implicit $exec
|
||||
# GCN: FLAT_STORE_DWORD %10, %16,
|
||||
|
||||
# GCN: %17:vgpr_32 = V_MOV_B32_e32 24, implicit $exec
|
||||
# GCN: FLAT_STORE_DWORD %10, %17,
|
||||
|
||||
# GCN: %18:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
|
||||
# GCN: FLAT_STORE_DWORD %10, %18,
|
||||
|
||||
# GCN: %19:vgpr_32 = V_MOV_B32_e32 24, implicit $exec
|
||||
# GCN: FLAT_STORE_DWORD %10, %19,
|
||||
|
||||
# GCN: %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
# GCN: FLAT_STORE_DWORD %10, %3,
|
||||
|
||||
# GCN: %20:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
|
||||
# GCN: FLAT_STORE_DWORD %10, %20,
|
||||
|
||||
# GCN: %21:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
|
||||
# GCN: FLAT_STORE_DWORD %10, %21,
|
||||
|
||||
# GCN: %22:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
|
||||
# GCN: FLAT_STORE_DWORD %10, %22,
|
||||
|
||||
# GCN: %23:vgpr_32 = V_MOV_B32_e32 7927808, implicit $exec
|
||||
# GCN: FLAT_STORE_DWORD %10, %23,
|
||||
|
||||
# GCN: %24:vgpr_32 = V_MOV_B32_e32 -8, implicit $exec
|
||||
# GCN: FLAT_STORE_DWORD %10, %24,
|
||||
|
||||
name: v_fold_shl_imm_regimm_32
|
||||
alignment: 0
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
tracksRegLiveness: true
|
||||
liveins:
|
||||
- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
|
||||
- { reg: '$vgpr0', virtual-reg: '%2' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0_sgpr1, $vgpr0
|
||||
|
||||
%2:vgpr_32 = COPY $vgpr0
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%3:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, addrspace 4)
|
||||
%15:vgpr_32 = V_ASHRREV_I32_e64 31, %2, implicit $exec
|
||||
%16:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %15, %subreg.sub1
|
||||
%17:vreg_64 = V_LSHLREV_B64 2, killed %16, implicit $exec
|
||||
%9:sreg_32_xm0 = COPY %3.sub1
|
||||
%21:vgpr_32 = V_ADD_I32_e32 %3.sub0, %17.sub0, implicit-def $vcc, implicit $exec
|
||||
%19:vgpr_32 = COPY killed %9
|
||||
%18:vgpr_32 = V_ADDC_U32_e32 %17.sub1, %19, implicit-def $vcc, implicit $vcc, implicit $exec
|
||||
%20:vreg_64 = REG_SEQUENCE %21, %subreg.sub0, killed %18, %subreg.sub1
|
||||
%10:vgpr_32 = V_MOV_B32_e32 9999, implicit $exec
|
||||
%24:vgpr_32 = V_MOV_B32_e32 3871, implicit $exec
|
||||
%6:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
|
||||
%7:sreg_32_xm0 = S_MOV_B32 1
|
||||
%27:sreg_32_xm0 = S_MOV_B32 -4
|
||||
%11:vgpr_32 = V_LSHLREV_B32_e64 12, %10, implicit $exec
|
||||
FLAT_STORE_DWORD %20, %11, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
|
||||
%12:vgpr_32 = V_LSHLREV_B32_e64 %7, 12, implicit $exec
|
||||
FLAT_STORE_DWORD %20, %12, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
|
||||
%13:vgpr_32 = V_LSHL_B32_e64 %7, 12, implicit $exec
|
||||
FLAT_STORE_DWORD %20, %13, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
|
||||
%14:vgpr_32 = V_LSHL_B32_e64 12, %7, implicit $exec
|
||||
FLAT_STORE_DWORD %20, %14, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
|
||||
%15:vgpr_32 = V_LSHL_B32_e64 12, %24, implicit $exec
|
||||
FLAT_STORE_DWORD %20, %15, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
|
||||
%22:vgpr_32 = V_LSHL_B32_e64 %6, 12, implicit $exec
|
||||
FLAT_STORE_DWORD %20, %22, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
|
||||
%23:vgpr_32 = V_LSHL_B32_e64 %6, 32, implicit $exec
|
||||
FLAT_STORE_DWORD %20, %23, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
|
||||
%25:vgpr_32 = V_LSHL_B32_e32 %6, %6, implicit $exec
|
||||
FLAT_STORE_DWORD %20, %25, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
|
||||
%26:vgpr_32 = V_LSHLREV_B32_e32 11, %24, implicit $exec
|
||||
FLAT_STORE_DWORD %20, %26, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
|
||||
%28:vgpr_32 = V_LSHL_B32_e32 %27, %6, implicit $exec
|
||||
FLAT_STORE_DWORD %20, %28, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
|
||||
S_ENDPGM 0
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
# GCN-LABEL: name: constant_fold_lshl_add_reg0_immreg_reg{{$}}
|
||||
# GCN: %2:vgpr_32 = COPY $vgpr0, implicit $exec
|
||||
# GCN-NEXT: S_ENDPGM
|
||||
|
||||
name: constant_fold_lshl_add_reg0_immreg_reg
|
||||
alignment: 0
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0
|
||||
|
||||
%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
%1:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
|
||||
%2:vgpr_32 = V_LSHL_ADD_U32 %0, %1, $vgpr0, implicit $exec
|
||||
S_ENDPGM 0, implicit %2
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
# GCN-LABEL: name: constant_fold_lshl_add_reg0_immreg_imm{{$}}
|
||||
# GCN: %2:vgpr_32 = V_MOV_B32_e32 10, implicit $exec
|
||||
# GCN-NEXT: S_ENDPGM
|
||||
|
||||
name: constant_fold_lshl_add_reg0_immreg_imm
|
||||
alignment: 0
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
|
||||
%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
%1:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
|
||||
%2:vgpr_32 = V_LSHL_ADD_U32 %0, %1, 10, implicit $exec
|
||||
S_ENDPGM 0, implicit %2
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
# GCN-LABEL: name: constant_fold_lshl_add_reg0_immreg_immreg{{$}}
|
||||
# GCN: %3:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec
|
||||
# GCN-NEXT: S_ENDPGM
|
||||
|
||||
name: constant_fold_lshl_add_reg0_immreg_immreg
|
||||
alignment: 0
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
|
||||
%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
%1:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
|
||||
%2:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec
|
||||
%3:vgpr_32 = V_LSHL_ADD_U32 %0, %1, %2, implicit $exec
|
||||
S_ENDPGM 0, implicit %3
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
# GCN-LABEL: name: constant_fold_and_or_reg0_immreg_reg{{$}}
|
||||
# GCN: %2:vgpr_32 = COPY $vgpr0, implicit $exec
|
||||
# GCN-NEXT: S_ENDPGM
|
||||
|
||||
name: constant_fold_and_or_reg0_immreg_reg
|
||||
alignment: 0
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0
|
||||
|
||||
%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
%1:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
|
||||
%2:vgpr_32 = V_AND_OR_B32 %0, %1, $vgpr0, implicit $exec
|
||||
S_ENDPGM 0, implicit %2
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
# GCN-LABEL: name: constant_fold_and_or_reg0_immreg_imm{{$}}
|
||||
# GCN: %2:vgpr_32 = V_MOV_B32_e32 10, implicit $exec
|
||||
# GCN-NEXT: S_ENDPGM
|
||||
|
||||
name: constant_fold_and_or_reg0_immreg_imm
|
||||
alignment: 0
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
|
||||
%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
%1:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
|
||||
%2:vgpr_32 = V_AND_OR_B32 %0, %1, 10, implicit $exec
|
||||
S_ENDPGM 0, implicit %2
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
# GCN-LABEL: name: constant_fold_and_or_reg0_immreg_immreg{{$}}
|
||||
# GCN: %3:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec
|
||||
# GCN-NEXT: S_ENDPGM
|
||||
|
||||
name: constant_fold_and_or_reg0_immreg_immreg
|
||||
alignment: 0
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
|
||||
%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
%1:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
|
||||
%2:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec
|
||||
%3:vgpr_32 = V_AND_OR_B32 %0, %1, %2, implicit $exec
|
||||
S_ENDPGM 0, implicit %3
|
||||
|
||||
...
|
||||
|
|
|
|||
Loading…
Reference in New Issue