From a193510da2af9a1f2d2e8f9f2f9a0f6bde513123 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 26 Nov 2015 06:30:42 +0000 Subject: [PATCH] Add type constraints to masked_load/masked_store to ensure the mask vector has the same number of elements as the other vectors. llvm-svn: 254137 --- llvm/include/llvm/Target/TargetSelectionDAG.td | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td index 1b199e9fcec6..fd0e04913300 100644 --- a/llvm/include/llvm/Target/TargetSelectionDAG.td +++ b/llvm/include/llvm/Target/TargetSelectionDAG.td @@ -205,11 +205,12 @@ def SDTIStore : SDTypeProfile<1, 3, [ // indexed store ]>; def SDTMaskedStore: SDTypeProfile<0, 3, [ // masked store - SDTCisPtrTy<0>, SDTCisVec<1>, SDTCisVec<2> + SDTCisPtrTy<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisSameNumEltsAs<1, 2> ]>; def SDTMaskedLoad: SDTypeProfile<1, 3, [ // masked load - SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisVec<2>, SDTCisSameAs<0, 3> + SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisVec<2>, SDTCisSameAs<0, 3>, + SDTCisSameNumEltsAs<0, 2> ]>; def SDTMaskedGather: SDTypeProfile<2, 3, [ // masked gather