maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[X86] Use Register/MCRegister in more places in X86 

This was a quick pass through some obvious places. I haven't tried the clang-tidy check.

I also replaced the zeroes in getX86SubSuperRegister with X86::NoRegister which is the real sentinel name.

Differential Revision: https://reviews.llvm.org/D66363

llvm-svn: 369151
This commit is contained in:
Craig Topper 2019-08-16 20:50:23 +00:00
parent 8191585b36
commit a17d1d2250
9 changed files with 45 additions and 43 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/lib/Target/X86/AsmParser/X86Operand.h
View File

@ -500,7 +500,7 @@ struct X86Operand final : public MCParsedAsmOperand {
void addGR32orGR64Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
unsigned RegNo = getReg();
MCRegister RegNo = getReg();
if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
RegNo = getX86SubSuperRegister(RegNo, 32);
Inst.addOperand(MCOperand::createReg(RegNo));

28
llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
View File

@ -594,13 +594,13 @@ extern "C" void LLVMInitializeX86TargetMC() {
createX86_64AsmBackend);
}
unsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size,
bool High) {
MCRegister llvm::getX86SubSuperRegisterOrZero(MCRegister Reg, unsigned Size,
bool High) {
switch (Size) {
default: return 0;
default: return X86::NoRegister;
case 8:
if (High) {
switch (Reg) {
switch (Reg.id()) {
default: return getX86SubSuperRegisterOrZero(Reg, 64);
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
return X86::SI;
@ -620,8 +620,8 @@ unsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size,
return X86::BH;
}
} else {
switch (Reg) {
default: return 0;
switch (Reg.id()) {
default: return X86::NoRegister;
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
return X86::AL;
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
@ -657,8 +657,8 @@ unsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size,
}
}
case 16:
switch (Reg) {
default: return 0;
switch (Reg.id()) {
default: return X86::NoRegister;
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
return X86::AX;
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
@ -693,8 +693,8 @@ unsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size,
return X86::R15W;
}
case 32:
switch (Reg) {
default: return 0;
switch (Reg.id()) {
default: return X86::NoRegister;
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
return X86::EAX;
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
@ -729,7 +729,7 @@ unsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size,
return X86::R15D;
}
case 64:
switch (Reg) {
switch (Reg.id()) {
default: return 0;
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
return X86::RAX;
@ -767,9 +767,9 @@ unsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size,
}
}
unsigned llvm::getX86SubSuperRegister(unsigned Reg, unsigned Size, bool High) {
unsigned Res = getX86SubSuperRegisterOrZero(Reg, Size, High);
assert(Res != 0 && "Unexpected register or VT");
MCRegister llvm::getX86SubSuperRegister(MCRegister Reg, unsigned Size, bool High) {
MCRegister Res = getX86SubSuperRegisterOrZero(Reg, Size, High);
assert(Res != X86::NoRegister && "Unexpected register or VT");
return Res;
}

7
llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
View File

@ -13,6 +13,7 @@
#ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H
#define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H
#include "llvm/MC/MCRegister.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/Support/DataTypes.h"
#include <string>
@ -111,12 +112,12 @@ createX86WinCOFFObjectWriter(bool Is64Bit);
/// Returns the sub or super register of a specific X86 register.
/// e.g. getX86SubSuperRegister(X86::EAX, 16) returns X86::AX.
/// Aborts on error.
unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false);
MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false);
/// Returns the sub or super register of a specific X86 register.
/// Like getX86SubSuperRegister() but returns 0 on error.
unsigned getX86SubSuperRegisterOrZero(unsigned, unsigned,
bool High = false);
MCRegister getX86SubSuperRegisterOrZero(MCRegister, unsigned,
bool High = false);
} // End llvm namespace

10
llvm/lib/Target/X86/X86FixupBWInsts.cpp
View File

@ -80,7 +80,7 @@ class FixupBWInstPass : public MachineFunctionPass {
/// destination register of the MachineInstr passed in. It returns true if
/// that super register is dead just prior to \p OrigMI, and false if not.
bool getSuperRegDestIfDead(MachineInstr *OrigMI,
unsigned &SuperDestReg) const;
Register &SuperDestReg) const;
/// Change the MachineInstr \p MI into the equivalent extending load to 32 bit
/// register if it is safe to do so. Return the replacement instruction if
@ -169,7 +169,7 @@ bool FixupBWInstPass::runOnMachineFunction(MachineFunction &MF) {
///
/// If so, return that super register in \p SuperDestReg.
bool FixupBWInstPass::getSuperRegDestIfDead(MachineInstr *OrigMI,
unsigned &SuperDestReg) const {
Register &SuperDestReg) const {
auto *TRI = &TII->getRegisterInfo();
Register OrigDestReg = OrigMI->getOperand(0).getReg();
@ -268,7 +268,7 @@ bool FixupBWInstPass::getSuperRegDestIfDead(MachineInstr *OrigMI,
MachineInstr *FixupBWInstPass::tryReplaceLoad(unsigned New32BitOpcode,
MachineInstr *MI) const {
unsigned NewDestReg;
Register NewDestReg;
// We are going to try to rewrite this load to a larger zero-extending
// load. This is safe if all portions of the 32 bit super-register
@ -295,11 +295,11 @@ MachineInstr *FixupBWInstPass::tryReplaceCopy(MachineInstr *MI) const {
auto &OldDest = MI->getOperand(0);
auto &OldSrc = MI->getOperand(1);
unsigned NewDestReg;
Register NewDestReg;
if (!getSuperRegDestIfDead(MI, NewDestReg))
return nullptr;
unsigned NewSrcReg = getX86SubSuperRegister(OldSrc.getReg(), 32);
Register NewSrcReg = getX86SubSuperRegister(OldSrc.getReg(), 32);
// This is only correct if we access the same subregister index: otherwise,
// we could try to replace "movb %ah, %al" with "movl %eax, %eax".

7
llvm/lib/Target/X86/X86FixupLEAs.cpp
View File

@ -552,11 +552,12 @@ FixupLEAPass::processInstrForSlow3OpLEA(MachineInstr &MI,
Segment.getReg() != X86::NoRegister)
return nullptr;
unsigned DstR = Dst.getReg();
Register DstR = Dst.getReg();
Register BaseR = Base.getReg();
Register IndexR = Index.getReg();
unsigned SSDstR =
(LEAOpcode == X86::LEA64_32r) ? getX86SubSuperRegister(DstR, 64) : DstR;
Register SSDstR =
(LEAOpcode == X86::LEA64_32r) ? Register(getX86SubSuperRegister(DstR, 64))
: DstR;
bool IsScale1 = Scale.getImm() == 1;
bool IsInefficientBase = isInefficientLEAReg(BaseR);
bool IsInefficientIndex = isInefficientLEAReg(IndexR);

12
llvm/lib/Target/X86/X86FrameLowering.cpp
View File

@ -1001,10 +1001,10 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF,
bool NeedsWinCFI = NeedsWin64CFI || NeedsWinFPO;
bool NeedsDwarfCFI =
!IsWin64Prologue && (MMI.hasDebugInfo() || Fn.needsUnwindTableEntry());
unsigned FramePtr = TRI->getFrameRegister(MF);
const unsigned MachineFramePtr =
Register FramePtr = TRI->getFrameRegister(MF);
const Register MachineFramePtr =
STI.isTarget64BitILP32()
? getX86SubSuperRegister(FramePtr, 64) : FramePtr;
? Register(getX86SubSuperRegister(FramePtr, 64)) : FramePtr;
Register BasePtr = TRI->getBaseRegister();
bool HasWinCFI = false;
@ -1080,7 +1080,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF,
int stackGrowth = -SlotSize;
// Find the funclet establisher parameter
unsigned Establisher = X86::NoRegister;
Register Establisher = X86::NoRegister;
if (IsClrFunclet)
Establisher = Uses64BitFramePtr ? X86::RCX : X86::ECX;
else if (IsFunclet)
@ -1615,9 +1615,9 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
DL = MBBI->getDebugLoc();
// standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
const bool Is64BitILP32 = STI.isTarget64BitILP32();
unsigned FramePtr = TRI->getFrameRegister(MF);
Register FramePtr = TRI->getFrameRegister(MF);
unsigned MachineFramePtr =
Is64BitILP32 ? getX86SubSuperRegister(FramePtr, 64) : FramePtr;
Is64BitILP32 ? Register(getX86SubSuperRegister(FramePtr, 64)) : FramePtr;
bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
bool NeedsWin64CFI =

16
llvm/lib/Target/X86/X86InstrInfo.cpp
View File

@ -664,7 +664,7 @@ inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
}
bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
unsigned Opc, bool AllowSP, unsigned &NewSrc,
unsigned Opc, bool AllowSP, Register &NewSrc,
bool &isKill, MachineOperand &ImplicitOp,
LiveVariables *LV) const {
MachineFunction &MF = *MI.getParent()->getParent();
@ -911,7 +911,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
// LEA can't handle ESP.
bool isKill;
unsigned SrcReg;
Register SrcReg;
MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
SrcReg, isKill, ImplicitOp, LV))
@ -947,7 +947,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
(Is64Bit ? X86::LEA64_32r : X86::LEA32r);
bool isKill;
unsigned SrcReg;
Register SrcReg;
MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
ImplicitOp, LV))
@ -970,7 +970,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
: (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
bool isKill;
unsigned SrcReg;
Register SrcReg;
MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
ImplicitOp, LV))
@ -1005,7 +1005,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
bool isKill;
unsigned SrcReg;
Register SrcReg;
MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
SrcReg, isKill, ImplicitOp, LV))
@ -1013,7 +1013,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
const MachineOperand &Src2 = MI.getOperand(2);
bool isKill2;
unsigned SrcReg2;
Register SrcReg2;
MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
SrcReg2, isKill2, ImplicitOp2, LV))
@ -1054,7 +1054,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
bool isKill;
unsigned SrcReg;
Register SrcReg;
MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
SrcReg, isKill, ImplicitOp, LV))
@ -1093,7 +1093,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
bool isKill;
unsigned SrcReg;
Register SrcReg;
MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
SrcReg, isKill, ImplicitOp, LV))

2
llvm/lib/Target/X86/X86InstrInfo.h
View File

@ -218,7 +218,7 @@ public:
/// Reference parameters are set to indicate how caller should add this
/// operand to the LEA instruction.
bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc,
unsigned LEAOpcode, bool AllowSP, Register &NewSrc,
bool &isKill, MachineOperand &ImplicitOp,
LiveVariables *LV) const;

4
llvm/lib/Target/X86/X86RegisterInfo.cpp
View File

@ -544,7 +544,7 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
"Stack realignment in presence of dynamic allocas is not supported with"
"this calling convention.");
unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), 64);
Register BasePtr = getX86SubSuperRegister(getBaseRegister(), 64);
for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true);
I.isValid(); ++I)
Reserved.set(*I);
@ -729,7 +729,7 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// register as source operand, semantic is the same and destination is
// 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
// Don't change BasePtr since it is used later for stack adjustment.
unsigned MachineBasePtr = BasePtr;
Register MachineBasePtr = BasePtr;
if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
MachineBasePtr = getX86SubSuperRegister(BasePtr, 64);